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1. 发明授权

US07807512B2 Semiconductor packages and methods of fabricating the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US07807512B2
公开(公告)日：2010-10-05
申请号：US12320916
申请日：2009-02-09
申请人： Teak-Hoon Lee , Pyoung-Wan Kim , Nam-Seog Kim , Chul-Yong Jang
发明人： Teak-Hoon Lee , Pyoung-Wan Kim , Nam-Seog Kim , Chul-Yong Jang
IPC分类号： H01L21/00 , H01L21/30 , H01L21/46
CPC分类号： H01L25/0657 , H01L21/568 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/32145 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/06524 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/15173 , H01L2924/15311 , H01L2924/15331 , H01L2224/82
摘要： A semiconductor package and module, and methods of fabricating the same are provided. A method of fabricating a semiconductor package may include bonding rear surfaces of first and second semiconductor chips to each other, each of the semiconductor chips having chip pads exposed on front surfaces. The method may also include forming an encapsulation portion configured to encapsulate side surfaces of the bonded semiconductor chips, forming via plugs configured to pass through the encapsulation portion, forming an insulating layer configured to expose surfaces of the chip pads and the via plugs on the exposed surfaces of the two semiconductor chips and surfaces of the encapsulation portion, and forming package pads on the exposed surfaces of the chip pads and the surfaces of the via plugs.
摘要翻译：提供半导体封装和模块及其制造方法。制造半导体封装的方法可以包括将第一和第二半导体芯片的后表面彼此粘合，每个半导体芯片具有在前表面上暴露的芯片焊盘。该方法还可以包括形成封装部分，该封装部分被配置为封装接合的半导体芯片的侧表面，形成穿过被配置成穿过封装部分的插塞，形成绝缘层，该绝缘层被配置成暴露在暴露的芯片焊盘和通孔塞上的表面两个半导体芯片的表面和封装部分的表面，以及在芯片焊盘和通孔塞的表面的暴露表面上形成封装焊盘。

2. 发明申请

US20090239336A1 Semiconductor packages and methods of fabricating the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20090239336A1
公开(公告)日：2009-09-24
申请号：US12320916
申请日：2009-02-09
申请人： Teak-Hoon Lee , Pyoung-Wan Kim , Nam-Seog Kim , Chul-Yong Jang
发明人： Teak-Hoon Lee , Pyoung-Wan Kim , Nam-Seog Kim , Chul-Yong Jang
IPC分类号： H01L21/98
CPC分类号： H01L25/0657 , H01L21/568 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/32145 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/06524 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/15173 , H01L2924/15311 , H01L2924/15331 , H01L2224/82
摘要： A semiconductor package and module, and methods of fabricating the same are provided. A method of fabricating a semiconductor package may include bonding rear surfaces of first and second semiconductor chips to each other, each of the semiconductor chips having chip pads exposed on front surfaces. The method may also include forming an encapsulation portion configured to encapsulate side surfaces of the bonded semiconductor chips, forming via plugs configured to pass through the encapsulation portion, forming an insulating layer configured to expose surfaces of the chip pads and the via plugs on the exposed surfaces of the two semiconductor chips and surfaces of the encapsulation portion, and forming package pads on the exposed surfaces of the chip pads and the surfaces of the via plugs.
摘要翻译：提供半导体封装和模块及其制造方法。制造半导体封装的方法可以包括将第一和第二半导体芯片的后表面彼此粘合，每个半导体芯片具有在前表面上暴露的芯片焊盘。该方法还可以包括形成封装部分，该封装部分被配置为封装接合的半导体芯片的侧表面，形成穿过被配置成穿过封装部分的插塞，形成绝缘层，该绝缘层被配置成暴露在暴露的芯片焊盘和通孔塞上的表面两个半导体芯片的表面和封装部分的表面，以及在芯片焊盘和通孔塞的表面的暴露表面上形成封装焊盘。

3. 发明授权

US08115324B2 Semiconductor module 有权
标题翻译：半导体模块
公开(公告)号：US08115324B2
公开(公告)日：2012-02-14
申请号：US12292196
申请日：2008-11-13
申请人： Sun-Won Kang , Young-Hee Song , Tae-Gyeong Chung , Nam-Seog Kim , Seung-Duk Baek
发明人： Sun-Won Kang , Young-Hee Song , Tae-Gyeong Chung , Nam-Seog Kim , Seung-Duk Baek
IPC分类号： H01L29/40
CPC分类号： H01L25/0657 , H01L24/06 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/85399 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.
摘要翻译：半导体模块可以包括在电路基板上具有第一裸片的电路基板和在第一裸片上的第二裸片。第一裸片可以包括在第一裸片的第一周边部分上的至少一个第一数据输入/输出焊盘和第三外围部分上的至少一个第一控制/地址焊盘，第三外围部分与第一外围部分的第一外围部分分离第一个死亡第二管芯可以包括在第二外围部分上的至少一个第二数据输入/输出焊盘和第四外围部分上的至少一个第二控制/地址焊盘。第二模具的第二周边部分在平面图中不与第一模具的第一周边部分重叠。第二模具的第四周边部分与第一模具的第三周边部分的至少一部分重叠。

4. 发明申请

US20100022051A1 Method of fabricating electronic device having stacked chips 有权
标题翻译：制造具有堆叠芯片的电子装置的方法
公开(公告)号：US20100022051A1
公开(公告)日：2010-01-28
申请号：US12458923
申请日：2009-07-28
申请人： Hae-Jung Yu , Eun-Chul Ahn , Tae-Gyeong Chung , Nam-Seog Kim
发明人： Hae-Jung Yu , Eun-Chul Ahn , Tae-Gyeong Chung , Nam-Seog Kim
IPC分类号： H01L21/50 , H01L21/56
CPC分类号： H01L21/565 , H01L23/5387 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/24226 , H01L2224/76155 , H01L2224/82102 , H01L2224/97 , H01L2225/06524 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2225/1064 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/15311 , H01L2224/82
摘要： A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer between the chips arranged in the row direction. Conductive interconnections are formed on the substrate having the grooves. The substrate is sawn along an odd- or even-numbered one of the grooves to be separated into a plurality of unit substrates. At least one of the separated unit substrates is folded along an unsawn groove of the grooves.
摘要翻译：提供一种制造具有堆叠芯片的电子设备的方法。该方法包括形成沿行方向布置的多个芯片和沿列方向布置的至少一个芯片。在芯片之间形成模制层。在沿行方向布置的芯片之间的成型层中形成凹槽。在具有凹槽的基板上形成导电互连。衬底沿着奇数或偶数编号的一个沟槽被锯切，以分离成多个单位衬底。分离的单元基板中的至少一个沿着凹槽的未开槽的凹槽折叠。

5. 发明授权

US06947336B2 Semiconductor device with impedance control circuit 失效
标题翻译：具有阻抗控制电路的半导体器件
公开(公告)号：US06947336B2
公开(公告)日：2005-09-20
申请号：US10410453
申请日：2003-04-08
申请人： Tae-Hyoung Kim , Uk-Rae Cho , Nam-Seog Kim
发明人： Tae-Hyoung Kim , Uk-Rae Cho , Nam-Seog Kim
IPC分类号： H03K19/0175 , G11C7/10 , G11C11/401 , G11C16/04
CPC分类号： G11C7/1057 , G11C7/1051 , G11C2207/105
摘要： A semiconductor device includes an output impedance control circuit, connected to a ZQ pad and an output buffer circuit, for controlling an impedance of the output buffer circuit according to an impedance of an external resistor connected with the ZQ pad.
摘要翻译：半导体器件包括连接到ZQ焊盘和输出缓冲电路的输出阻抗控制电路，用于根据与ZQ焊盘连接的外部电阻器的阻抗来控制输出缓冲电路的阻抗。

6. 发明授权

US06930508B2 Integrated circuit with on-chip termination 有权
标题翻译：具有片上终端的集成电路
公开(公告)号：US06930508B2
公开(公告)日：2005-08-16
申请号：US10626015
申请日：2003-07-24
申请人： Nam-Seog Kim , Uk-Rae Cho , Tae-Hyoung Kim
发明人： Nam-Seog Kim , Uk-Rae Cho , Tae-Hyoung Kim
IPC分类号： H03H11/40 , H03B1/00 , H03K19/003 , H04L25/02
CPC分类号： H04L25/0278
摘要： There is provided an integrated circuit which performs data input/output operations through a transmission line with a predetermined impedance. The integrated circuit includes a driver having a plurality of driving units, in which the driving units input/output data from/to the transmission line, and a controller for inputting an output data signal and applying a plurality of control signals to the driver, in which the control signals are generated in response to an output activation signal and impedance code signals related to states of the impedance. At least one driving unit is driven in response to the control signals, and the driver includes an on-chip termination circuit connected to an input buffer.
摘要翻译：提供了通过具有预定阻抗的传输线执行数据输入/输出操作的集成电路。集成电路包括具有多个驱动单元的驱动器，其中驱动单元从/向传输线输入/输出数据，以及用于输入输出数据信号并将多个控制信号施加到驾驶员的控制器，其响应于与阻抗状态相关的输出激活信号和阻抗代码信号而产生控制信号。响应于控制信号驱动至少一个驱动单元，并且驱动器包括连接到输入缓冲器的片上终端电路。

7. 发明申请

US20050146365A1 Apparatus for generating internal clock signal 失效
标题翻译：用于产生内部时钟信号的装置
公开(公告)号：US20050146365A1
公开(公告)日：2005-07-07
申请号：US11031129
申请日：2005-01-07
申请人： Nam-Seog Kim , Yong-Jin Yoon , Uk-Rae Cho
发明人： Nam-Seog Kim , Yong-Jin Yoon , Uk-Rae Cho
IPC分类号： G11C11/40 , G11C7/00 , G11C8/00 , G11C11/407 , H03K5/13 , H03K5/135 , H03L7/06 , H03L7/081
CPC分类号： H03L7/0812 , H03K5/133 , H03K5/135
摘要： An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal; a forward delay array; a mirror control circuit comprising a plurality of phase detectors for detecting delayed clock signals synchronized with a second reference clock signal; a backward delay array; and an output buffer to generate an internal clock signal. An internal clock signal in accurate synchronization with the reference clock signal can be generated by minimizing the delay and distortion of the reference clock signal.
摘要翻译：提供一种用于产生用于获取精确同步的内部时钟信号的装置。该装置包括：输入缓冲器，用于缓冲外部时钟信号以输出第一参考时钟信号; 延迟补偿电路，用于延迟第一参考时钟信号; 前向延迟阵列镜控制电路，包括用于检测与第二参考时钟信号同步的延迟时钟信号的多个相位检测器; 后向延迟阵列以及产生内部时钟信号的输出缓冲器。可以通过最小化参考时钟信号的延迟和失真来产生与参考时钟信号精确同步的内部时钟信号。

8. 发明申请

US20050104222A1 Flip chip device having supportable bar and mounting structure thereof 审中-公开
标题翻译：具有可支撑杆及其安装结构的倒装芯片装置
公开(公告)号：US20050104222A1
公开(公告)日：2005-05-19
申请号：US10944613
申请日：2004-09-20
申请人： Se-Young Jeong , Gu-Sung Kim , Nam-Seog Kim , Gi-Hwan Park , Se-Yong Oh , Soon-Bum Kim , In-Young Lee
发明人： Se-Young Jeong , Gu-Sung Kim , Nam-Seog Kim , Gi-Hwan Park , Se-Yong Oh , Soon-Bum Kim , In-Young Lee
IPC分类号： H01L23/28 , H01L21/60 , H01L23/16 , H01L23/31 , H01L23/485 , H01L23/498 , H05K3/34 , H01L23/48
CPC分类号： H01L24/13 , H01L23/16 , H01L23/3114 , H01L23/49838 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/0401 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05647 , H01L2224/05655 , H01L2224/06102 , H01L2224/13076 , H01L2224/13082 , H01L2224/13111 , H01L2224/13113 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2224/1357 , H01L2224/13611 , H01L2224/1403 , H01L2224/14051 , H01L2224/14131 , H01L2224/14136 , H01L2224/14155 , H01L2224/16 , H01L2224/1601 , H01L2224/29011 , H01L2224/29013 , H01L2224/29076 , H01L2224/30155 , H01L2224/30156 , H01L2224/73103 , H01L2224/73203 , H01L2224/81141 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/351 , H05K3/3436 , H05K2201/094 , H05K2203/0465 , Y02P70/613 , H01L2924/00014 , H01L2924/01028 , H01L2924/01083 , H01L2224/13099 , H01L2924/00012 , H01L2924/3512 , H01L2924/00 , H01L2924/013
摘要： A flip chip device may have a semiconductor chip with an active surface on which chip pads and a protective layer may be provided. Solder bumps may be provided on the active surface and electrically connected to the chip pads. And a solder bar may be provided on a portion of the protective layer. The solder bar may disperse thermal stress produced in the solder bumps. A metal core may be embedded within the solder bar. The flip chip device may be mounted on and flip-chip bonded to a substrate. The substrate may have land pads to which the solder bumps and the solder bar may be mechanically joined. The solder bar increases a joint area between the flip chip device and the substrate and reinforces solder connections therebetween.
摘要翻译：倒装芯片器件可以具有其上可以设置有芯片焊盘和保护层的有源表面的半导体芯片。可以在活性表面上提供焊料凸块并电连接到芯片焊盘。并且可以在保护层的一部分上设置焊料条。焊料棒可能会分散焊料凸点产生的热应力。金属芯可以嵌入在焊条内。倒装芯片器件可以安装在衬底上并倒装芯片结合到衬底上。衬底可以具有焊盘，焊盘和焊条可以焊接到其上。焊条增加了倒装芯片器件和衬底之间的接合面积，并加强了它们之间的焊接连接。

9. 发明授权

US06806763B2 Programmable reference voltage generating circuit 失效
标题翻译：可编程参考电压发生电路
公开(公告)号：US06806763B2
公开(公告)日：2004-10-19
申请号：US10059676
申请日：2002-01-30
申请人： Nam-Seog Kim , Jin-Ho Lee
发明人： Nam-Seog Kim , Jin-Ho Lee
IPC分类号： G05F110
CPC分类号： G05F1/577
摘要： A reference voltage generating circuit includes a binary-to-thermometer for converting binary codes into thermometer codes; an internal reference voltage generator for generating an internal reference voltage in response to the thermometer codes from the binary-to-thermometer, wherein the internal reference voltage generator changes a level of the internal reference voltage in response to the thermometer codes; a selector for selecting the internal reference voltage or an external reference voltage in response to a reference voltage select signal; and a voltage regulator for regulating a reference voltage selected by the selector.
摘要翻译：参考电压产生电路包括用于将二进制码转换成温度计代码的二进制到温度计; 内部参考电压发生器，用于响应于二进制到温度计的温度计代码产生内部参考电压，其中内部参考电压发生器响应于温度计代码改变内部参考电压的电平; 用于响应于参考电压选择信号选择内部参考电压或外部参考电压的选择器; 以及用于调节由选择器选择的参考电压的电压调节器。

10. 发明授权

US06642740B2 Programmable termination circuit and method 有权
公开(公告)号：US06642740B2
公开(公告)日：2003-11-04
申请号：US09933102
申请日：2001-08-20
申请人： Nam-Seog Kim , Uk-Rae Cho
发明人： Nam-Seog Kim , Uk-Rae Cho
IPC分类号： H03K19003
CPC分类号： H03K19/0005
摘要： A semiconductor device is provided which includes: a plurality of termination circuits having a plurality of impedance elements connected to an input/output pad, said termination circuits being controlled by impedance control signals; and a controller for outputting said impedance control signals to adaptively change with changes in characteristic impedance of a transmission line connected to the input/output pad in bi-directional data communication, to adaptively control the plurality of impedance elements in the plurality of input termination circuits for matching the impedance to the characteristic impedance of the transmission line. Each of the plurality of impedance elements is configured in pairs of MOS transistors. The plurality of termination circuits have different impedance values. And each of the impedance elements of the plurality of termination circuits is independently controlled.

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