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1. 发明授权

US6137140A Integrated SCR-LDMOS power device 有权
标题翻译：集成SCR-LDMOS电源设备
公开(公告)号：US6137140A
公开(公告)日：2000-10-24
申请号：US196826
申请日：1998-11-20
申请人： Taylor Rice Efland , Stephen C. Kwan , Kenneth G. Buss , Chin-Yu Tsai
发明人： Taylor Rice Efland , Stephen C. Kwan , Kenneth G. Buss , Chin-Yu Tsai
IPC分类号： H01L27/07 , H01L29/74 , H01L29/76
CPC分类号： H01L29/742 , H01L27/0711 , H01L29/7436
摘要： An integrated SCR-LDMOS device (10) having a p+ region (13) in the drain region (12), but otherwise similar to a conventional LDMOS transistor. The device (10) may be implemented as a modification of a non-planar LDMOS (FIGS. 1 and 2). An alternate embodiment, device (30), may be implemented as a modification of a planar LDMOS (FIG. 3). In either case, the added p+ region (13, 37) provides the device (10, 30) with two parasitic bipolar transistors in an SCR configuration (FIGS. 4A and 4B).
摘要翻译：在漏区（12）中具有p +区（13）的集成SCR-LDMOS器件（10），但是与常规LDMOS晶体管类似。设备（10）可以被实现为非平面LDMOS（图1和图2）的修改。替代实施例，装置（30）可以被实现为平面LDMOS（图3）的修改。在任一种情况下，添加的p +区（13,37）在SCR配置中提供具有两个寄生双极晶体管（图4A和4B）的器件（10,30）。

2. 发明授权

US06753575B2 Tank-isolated-drain-extended power device 有权
标题翻译：储罐隔离漏极扩展功率器件
公开(公告)号：US06753575B2
公开(公告)日：2004-06-22
申请号：US10167159
申请日：2002-06-11
申请人： Taylor R. Efland , Chin-Yu Tsai
发明人： Taylor R. Efland , Chin-Yu Tsai
IPC分类号： H10L31119
CPC分类号： H01L21/765 , H01L21/761 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.
摘要翻译：一个槽隔离漏极扩展功率器件（50,60,70,80），其具有与p型Dwell（32）组合的附加横向延伸的重掺杂p型区域（56,62,72），其减少少数载流子积聚。 p掺杂区域限定在由与形成防护层的深低电阻漏极区域（16）连接的掩埋NBL区域（14）围绕的P外延层中。这种额外的横向延伸的p掺杂区域（56,62,72）减少了少数载流子的积累，使得恢复时间显着降低，并且由于少数载流子的收集时间减少，功率损耗也显着降低。该器件可以形成为LDMOS器件。

3. 发明授权

US06512280B2 Integrated CMOS structure for gate-controlled buried photodiode 有权
公开(公告)号：US06512280B2
公开(公告)日：2003-01-28
申请号：US09859121
申请日：2001-05-16
申请人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
发明人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
IPC分类号： H01L31072
CPC分类号： H01L31/112 , H01L27/1463 , H01L27/148
摘要： A light-sensing diode fabricated in a semiconductor substrate having a surface protected by an insulator, comprising a first region of one conductivity type in this substrate, a second region of the opposite conductivity type forming a junction with the first region in the substrate; this junction having a convoluted shape, providing two portions generally parallel to the surface, and a constricted intersection with the surface; and a gate for applying electrical bias across the junction, this gate positioned on the insulator such that it covers all portions of the junction intersection with the surface, thereby creating a gate-controlled photodiode.

4. 发明授权

US06710427B2 Distributed power device with dual function minority carrier reduction 有权
标题翻译：具有双功能少数载波减少的分布式功率器件
公开(公告)号：US06710427B2
公开(公告)日：2004-03-23
申请号：US10167136
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , David D. Briggs , Dale Skelton
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , David D. Briggs , Dale Skelton
IPC分类号： H01L2900
CPC分类号： H01L29/1083 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/7835
摘要： A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D4) between the NBL layer and the substrate will never be forward biased. In addition, each of the tank regions has a heavily doped p-type region (56) reducing the minority carrier lifetime to provide increased switching speed of the large power FET.
摘要翻译：一种分布式功率器件（100），包括通过深n型区域（16）彼此分离的多个槽区（90），并且在每个槽区中形成有多个晶体管（50）。每个槽区中的多个晶体管（50）与其它罐区中的晶体管相互连接以形成大功率FET，由此深n型区域将罐区彼此隔离。第一寄生二极管（D5）从每个槽区限定到埋层，并且在掩埋层和衬底之间限定第二寄生二极管（D4）。深n型区域相对于多个罐区域分布第一和第二寄生二极管，优选地由P-epi罐组成。深n型区域还分布形成在罐区域下方的NBL层（14）的电阻。分布式寄生二极管和NBL层的电阻有利地提供NBL层和衬底之间的寄生二极管（D4）将永远不会被正向偏置。此外，每个槽区具有重掺杂的p型区（56），减少了少量载流子寿命，以提供大功率FET的提高的开关速度。

5. 发明授权

US06621064B2 CMOS photodiode having reduced dark current and improved light sensitivity and responsivity 有权
标题翻译： CMOS光电二极管具有降低的暗电流和改善的光敏度和响应性
公开(公告)号：US06621064B2
公开(公告)日：2003-09-16
申请号：US09848637
申请日：2001-05-03
申请人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
发明人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
IPC分类号： H01L3100
CPC分类号： H01L31/1126 , H01L27/14643 , H01L27/148
摘要： A light-sensing diode having improved efficiency due to an extended junction geometry that provides more than one level of interaction with the light input.
摘要翻译：一种感光二极管，由于延长的接合几何形状而提高了效率，提供了与光输入不止一个层次的交互作用。

6. 发明授权

US06806541B2 Field effect transistor with improved isolation structures 有权
公开(公告)号：US06806541B2
公开(公告)日：2004-10-19
申请号：US10791172
申请日：2004-03-01
申请人： Lily X. Springer , Binghua Hu , Chin-Yu Tsai , Jozef C. Mitros
发明人： Lily X. Springer , Binghua Hu , Chin-Yu Tsai , Jozef C. Mitros
IPC分类号： H01L2976
CPC分类号： H01L21/76216
摘要： An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.

7. 发明授权

US06729886B2 Method of fabricating a drain isolated LDMOS device 有权
标题翻译：制造漏极隔离LDMOS器件的方法
公开(公告)号：US06729886B2
公开(公告)日：2004-05-04
申请号：US10167283
申请日：2002-06-11
申请人： Taylor R. Efland , Chin-Yu Tsai
发明人： Taylor R. Efland , Chin-Yu Tsai
IPC分类号： H01L218238
CPC分类号： H01L21/761 , H01L29/1083 , H01L29/7835
摘要： A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.
摘要翻译：一个槽隔离漏极扩展功率器件（50,60,70,80），其具有与p型Dwell（32）组合的附加横向延伸的重掺杂p型区域（56,62,72），其减少少数载流子积聚。 p掺杂区域限定在由与形成防护层的深低电阻漏极区域（16）连接的掩埋NBL区域（14）围绕的P外延层中。这种额外的横向延伸的p掺杂区域（56,62,72）减少了少数载流子的积累，使得恢复时间显着降低，并且由于少数载流子的收集时间减少，功率损耗也显着降低。该器件可以形成为LDMOS器件。

8. 发明授权

US06709900B2 Method of fabricating integrated system on a chip protection circuit 有权
标题翻译：在芯片保护电路上制造集成系统的方法
公开(公告)号：US06709900B2
公开(公告)日：2004-03-23
申请号：US10166964
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
IPC分类号： H01L21332
CPC分类号： H01L29/1083 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/7835
摘要： A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.
摘要翻译：一种功率集成电路架构（10），其具有插入在控制电路（152）和低侧晶体管（100）之间的高侧晶体管（100），以降低所述低侧晶体管对所述控制电路的操作的影响。低侧晶体管具有高p掺杂区域（56），其被设计为减少少数载流子寿命并改善少数载流子收集以减少少数载流子扰乱控制电路。低侧晶体管具有被连接到模拟地的保护（16），由此将控制电路连接到数字地，使得将少数载流子收集到模拟地中不会干扰控制电路的操作。低侧晶体管包括由至少一个深n型区域（16）分隔的多个晶体管阵列（90），该深n型区域围绕相应的晶体管阵列形成保护。防护器将一个晶体管阵列中的少数载流子与另一晶体管阵列隔离，并且便于通过其中的少数载流子的收集。

9. 发明授权

US06680226B2 Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology 有权
标题翻译：在深亚微米技术中优化数字和模拟CMOS晶体管性能的方法和设备
公开(公告)号：US06680226B2
公开(公告)日：2004-01-20
申请号：US10230559
申请日：2002-08-29
申请人： Taylor R. Efland , Alec J. Morton , Chin-Yu Tsai
发明人： Taylor R. Efland , Alec J. Morton , Chin-Yu Tsai
IPC分类号： H01L218238
CPC分类号： H01L21/823412 , H01L27/088
摘要： High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket regions (134) for optimum performance. These pocket regions (134) are masked from at least the drain side of the analog transistors (144, 146) to provide a flat channel doping profile on the drain side. Second pocket regions (200) may be formed in the analog transistors. The flat channel doping profile provides high early voltage and higher gain.
摘要翻译：高性能数字晶体管（140）和模拟晶体管（144,146）同时形成。数字晶体管（140）包括用于最佳性能的第一口袋区域（134）。从模拟晶体管（144,146）的至少漏极侧对这些凹区（134）进行掩模，以在漏极侧提供平坦的沟道掺杂分布。第二袋区（200）可以形成在模拟晶体管中。平坦沟道掺杂分布提供高的早期电压和更高的增益。

10. 发明授权

US06441431B1 Lateral double diffused metal oxide semiconductor device 有权
公开(公告)号：US06441431B1
公开(公告)日：2002-08-27
申请号：US09454934
申请日：1999-12-03
申请人： Taylor Efland , Chin-Yu Tsai , Sameer Pendharkar
发明人： Taylor Efland , Chin-Yu Tsai , Sameer Pendharkar
IPC分类号： H01L2976
CPC分类号： H01L29/66537 , H01L29/086 , H01L29/0878 , H01L29/1045 , H01L29/1095 , H01L29/42368 , H01L29/517 , H01L29/518 , H01L29/7816 , H01L29/7833
摘要： An embodiment of the instant invention is a transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region (well 204 of FIG. 1a) formed in the semiconductor substrate (layer 202 of FIG. 1a), the well region of a second conductivity type opposite that of the first conductivity type; a source region (source region 208 of FIG. 1a) formed in the well region in the semiconductor substrate, the source region of the second conductivity type; a drain region (drain 210 of FIG. 1a) formed in the semiconductor substrate and spaced away from the source region by a channel region (given by length L1+L2), the drain region of the second conductivity type; a conductive gate electrode (layer 218 of FIG. 1a) disposed over the semiconductor substrate and over the channel region; a gate insulating layer (layer 214 of FIG. 1a) disposed between the conductive gate electrode and the semiconductor substrate and having a length, the gate insulating layer comprising: a first portion of the gate insulating layer which has a first length (L1) and a first thickness; a second portion of the gate insulating layer which has a second length (L2) and a second thickness which is substantially thicker than the first thickness, the sum of the first length and the second length equalling the length of the gate insulating layer; and wherein the first portion of the gate insulating layer being situated proximate to the source region and spaced away from the drain region by the second portion of the gate insulating layer; and wherein the well region having a dopant concentration less than that of the source region and the drain region, the well region extends at least from source region towards the drain region so as to completely underlie the first portion of the gate insulating layer and to underlie at least the second portion of the gate insulating layer.

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