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1. 发明授权

US07898305B2 PLL circuit 有权
标题翻译： PLL电路
公开(公告)号：US07898305B2
公开(公告)日：2011-03-01
申请号：US12651061
申请日：2009-12-31
申请人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
发明人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/1976
摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).
摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号（26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

2. 发明授权

US07746132B2 PLL circuit 有权
标题翻译： PLL电路
公开(公告)号：US07746132B2
公开(公告)日：2010-06-29
申请号：US12066000
申请日：2006-07-27
申请人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
发明人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/1976
摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).
摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号（26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

3. 发明申请

US20100171533A1 PLL CIRCUIT 有权
标题翻译： PLL电路
公开(公告)号：US20100171533A1
公开(公告)日：2010-07-08
申请号：US12651061
申请日：2009-12-31
申请人： Tatsuo OKAMOTO , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
发明人： Tatsuo OKAMOTO , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/1976
摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).
摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号（26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

4. 发明申请

US20090153203A1 PLL CIRCUIT 有权
标题翻译： PLL电路
公开(公告)号：US20090153203A1
公开(公告)日：2009-06-18
申请号：US12066000
申请日：2006-07-27
申请人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
发明人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/1976
摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).
摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号（26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

5. 发明申请

US20110115531A1 PLL CIRCUIT 审中-公开
标题翻译： PLL电路
公开(公告)号：US20110115531A1
公开(公告)日：2011-05-19
申请号：US13014362
申请日：2011-01-26
申请人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
发明人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
IPC分类号： H03L7/095 , H03B19/00 , H03L7/10
CPC分类号： H03L7/10 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/1976
摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).
摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号（26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

6. 发明申请

US20050135505A1 Frequency modulation circuit 有权
标题翻译：频率调制电路
公开(公告)号：US20050135505A1
公开(公告)日：2005-06-23
申请号：US11000224
申请日：2004-12-01
申请人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Yukio Arima
发明人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Yukio Arima
IPC分类号： H03C3/00 , H03K7/06 , H03L7/093 , H04B15/02 , H04B3/46
CPC分类号： H04B15/02 , H03K7/06 , H04B2215/067
摘要： The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.
摘要翻译：频率调制电路包括：相移部，用于接收由多个时钟信号组成的多相时钟信号，所述多个时钟信号具有预定的相位差，并移位多相时钟信号的相位; 时钟选择部分，用于选择构成从相移部分输出的多相时钟信号的时钟信号; 以及调制控制部分，用于控制相移部分和时钟选择部分，使得从时钟选择部分输出具有与输入到相移部分的多相时钟信号的频率不同的频率的时钟信号。

7. 发明申请

US20110164693A1 INTERFACE CIRCUIT 审中-公开
标题翻译：接口电路
公开(公告)号：US20110164693A1
公开(公告)日：2011-07-07
申请号：US13047337
申请日：2011-03-14
申请人： Yoshihide KOMATSU , Tsuyoshi Ebuchi , Yukio Arima , Toru Iwata
发明人： Yoshihide KOMATSU , Tsuyoshi Ebuchi , Yukio Arima , Toru Iwata
IPC分类号： H04L27/00
CPC分类号： H04L7/0008 , G06F1/12 , H04L5/1469 , H04L5/16 , H04L25/0272 , H04L25/0298
摘要： An interface circuit including an LSI (10) in a host device (1), and an LSI (20) in a sub device (2), respectively. The LSI (10) generates a first transmission clock signal (TC1) and a first reception clock signal (RC1) separately in accordance with a first reference clock signal (RFC1). The LSI (10) also generates a second reference clock signal (RFC2) for a sub device (2). The reference clock signal (RFC2) is converted into a differential clock signal, and then transmitted to the sub device (2). An LSI (20) of the sub device (2) generates a second transmission clock signal (TC2) and a second reception clock signal (RC2) separately in accordance with a third reference clock signal (RFC3) converted from the differential clock signal.
摘要翻译：一种在主机（1）中包括LSI（10）的接口电路和分装置（2）中的LSI（20）。 LSI（10）根据第一参考时钟信号（RFC1）分别产生第一传输时钟信号（TC1）和第一接收时钟信号（RC1）。 LSI（10）还为子设备（2）生成第二参考时钟信号（RFC2）。参考时钟信号（RFC2）被转换为差分时钟信号，然后发送到子设备（2）。子装置（2）的LSI（20）根据从差分时钟信号转换的第三参考时钟信号（RFC3）分别产生第二传输时钟信号（TC2）和第二接收时钟信号（RC2）。

8. 发明授权

US07233215B2 Frequency modulation circuit 有权
标题翻译：频率调制电路
公开(公告)号：US07233215B2
公开(公告)日：2007-06-19
申请号：US11000224
申请日：2004-12-01
申请人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Yukio Arima
发明人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Yukio Arima
IPC分类号： H03C3/00
CPC分类号： H04B15/02 , H03K7/06 , H04B2215/067
摘要： The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.
摘要翻译：频率调制电路包括：相移部，用于接收由多个时钟信号组成的多相时钟信号，所述多个时钟信号具有预定的相位差，并移位多相时钟信号的相位; 时钟选择部分，用于选择构成从相移部分输出的多相时钟信号的时钟信号; 以及调制控制部分，用于控制相移部分和时钟选择部分，使得从时钟选择部分输出具有与输入到相移部分的多相时钟信号的频率不同的频率的时钟信号。

9. 发明授权

US5293326A Ultrasonic inspection and imaging instrument 失效
标题翻译：超声波检查和成像仪器
公开(公告)号：US5293326A
公开(公告)日：1994-03-08
申请号：US719510
申请日：1991-06-24
申请人： Yukio Arima , Hiroaki Yanagimoto , Yuichi Kunitomo , Shouya Makihara , Tetsuyoshi Tominaga
发明人： Yukio Arima , Hiroaki Yanagimoto , Yuichi Kunitomo , Shouya Makihara , Tetsuyoshi Tominaga
IPC分类号： G01N29/06 , G01N29/44 , G01Q10/06 , G01Q30/04 , G01Q80/00 , G01Q90/00 , G01S7/52 , G01N29/00 , G09G5/00
CPC分类号： G01S7/52074 , G01N29/0609 , G01N29/0645 , B82Y35/00 , G01N2291/02854
摘要： An ultrasonic inspection and imaging instrument is characterized by storing reduced image examples (images by means of reduced image display data obtained by scaling down picture display data) of an ultrasonic measurement picture beforehand, together with measurement conditions at the time the measurement picture is obtained prior to a scale-down imaging process. When the measurement is started or the measurement conditions are otherwise changed, the measurement conditions are set as those obtained from the measurement picture prior to the scale-down processing with one of the reduced image examples thus selected as an index while a list of image examples is indicated on a display and read from a memory unit for ultrasonic measuring purposes. When a reduced image example or what is similar to the example desired by an operator is selected, proper measurement conditions are automatically set in the ultrasonic inspection and imaging instrument. When the operator wants to change or switch the measurement picture, moreover, he/she is able to make ultrasonic measurement on confirming what the subsequent image is like or what an image is desired to be selected by means of the reduced image example beforehand.
摘要翻译：超声波检查和成像仪器的特征在于预先存储超声波测量图像的缩小图像示例（通过缩小图像显示数据获得的缩小图像显示数据的图像）以及在获得测量图像时的测量条件到缩小成像过程。当测量开始或测量条件另外改变时，测量条件被设置为在缩小处理之前从测量图像获得的测量条件，其中一个缩小图像示例被选择为索引，而图像示例列表在显示器上指示并从用于超声波测量目的的存储器单元读取。当选择缩小的图像示例或类似于操作者期望的示例时，在超声波检查和成像仪器中自动设置适当的测量条件。此外，当操作者想要改变或切换测量图像时，他/她能够通过预先通过缩小的图像实例来确认随后的图像是什么样的或希望选择什么图像来进行超声波测量。

10. 发明授权

US08300755B2 Timing recovery circuit, communication node, network system, and electronic device 有权
标题翻译：定时恢复电路，通信节点，网络系统和电子设备
公开(公告)号：US08300755B2
公开(公告)日：2012-10-30
申请号：US12602751
申请日：2007-11-30
申请人： Yukio Arima
发明人： Yukio Arima
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/089 , H03L7/091
摘要： A comparison period determiner (110) detects whether or not a change occurs in received data during a comparison period including a timing at which a rising edge of a reference clock occurs. A phase determiner (120) determines whether a rising edge of the received data is located before or after the reference clock and determines whether a falling edge of the received data is located before or after the reference clock, and outputs a first determination signal and a second determination signal indicating results of the respective determinations. A synchronous data generator (130) outputs a signal having a level depending on a result of the detection by the comparison period determiner (110) and an output of the phase determiner (120), as synchronous data, in synchronization with a synchronization clock.
摘要翻译：比较周期确定器（110）在包括参考时钟的上升沿出现的定时的比较周期中检测接收数据是否发生变化。相位确定器（120）确定接收数据的上升沿是否位于参考时钟之前或之后，并且确定接收数据的下降沿是否位于参考时钟之前或之后，并输出第一确定信号和指示各个确定的结果的第二确定信号。同步数据生成器（130）与同步时钟同步地输出具有比较周期确定器（110）的检测结果的电平和相位确定器（120）的输出作为同步数据的信号。

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