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1. 发明授权

US5060191A Ferroelectric memory 失效
标题翻译：铁电存储器
公开(公告)号：US5060191A
公开(公告)日：1991-10-22
申请号：US373082
申请日：1989-06-28
申请人： Tatsuo Nagasaki , Masayoshi Omura , Hitoshi Watanabe , Shinichi Imade , Eishi Ikuta , Hiroyuki Yoshimori , Kazuhisa Yanagisawa
发明人： Tatsuo Nagasaki , Masayoshi Omura , Hitoshi Watanabe , Shinichi Imade , Eishi Ikuta , Hiroyuki Yoshimori , Kazuhisa Yanagisawa
IPC分类号： G11B9/02 , G11C11/22 , G11C11/42 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/28 , H01L51/05
CPC分类号： G11C11/22
摘要： A ferroelectric memory includes a ferroelectric thin film having first and second surfaces opposite to each other, a first electrode assembly having a plurality of stripe electrodes arranged in parallel on the first surface side of the ferroelectric thin film, a second electrode assembly having a plurality of stripe electrodes arranged in parallel on the second surface side of the ferroelectric thin film to intersect the stripe electrodes of said first electrode assembly, first and second common electrodes arranged separately from the end portions of the respective first and second electrode assemblies to extend in respective directions in which the stripe electrodes of the first and second electrode assemblies are arranged, and selecting sections for respectively connecting the first and second electrode assemblies to the first and second common electrodes and selectively activating at least one of the stripe electrodes of each of the first and second electrode assemblies.
摘要翻译：铁电存储器包括具有彼此相对的第一和第二表面的铁电薄膜，具有在铁电薄膜的第一表面侧平行布置的多个条状电极的第一电极组件，具有多个在铁电薄膜的第二表面侧平行布置的条状电极与所述第一电极组件的条形电极相交，与各个第一和第二电极组件的端部分开布置的第一和第二公共电极在各个方向上延伸其中布置有第一和第二电极组件的条形电极，以及选择部分，用于分别将第一和第二电极组件连接到第一和第二公共电极，并且选择性地激活第一和第二电极组中的每一个的条形电极中的至少一个，第二电极组件。

2. 发明授权

US5541870A Ferroelectric memory and non-volatile memory cell for same 失效
标题翻译：铁电存储器和非易失性存储器单元相同
公开(公告)号：US5541870A
公开(公告)日：1996-07-30
申请号：US330989
申请日：1994-10-28
申请人： Takashi Mihara , Hitoshi Watanabe , Hiroyuki Yoshimori , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Takashi Mihara , Hitoshi Watanabe , Hiroyuki Yoshimori , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： G11C17/00 , G11C11/22 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11502 , G11C11/22
摘要： A non-volatile integrated circuit memory in which the memory cell includes a first transistor gate overlying a first channel region, a ferroelectric material overlying a second channel region, and a second transistor gate overlying a third channel region. The channel regions are connected in series, and preferably are contiguous portions of a single semiconducting channel. The firm channel is connected to a plate voltage that is 20% to 50% of the coercive voltage of the ferroelectric material. A sense amplifier is connected to the third channel region via a bit line. The rise of the bit line after reading a logic "1" state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.
摘要翻译：一种非易失性集成电路存储器，其中存储单元包括覆盖第一沟道区的第一晶体管栅极，覆盖第二沟道区的铁电材料和覆盖第三沟道区的第二晶体管栅极。通道区域串联连接，优选地是单个半导体通道的连续部分。固体通道连接到铁电体的矫顽电压的20％至50％的板电压。读出放大器通过位线连接到第三通道区域。读出逻辑“1”状态之后的位线的上升通过在读出放大器上升之前切断第三通道来防止铁电材料的干扰。

3. 发明授权

US5466629A Process for fabricating ferroelectric integrated circuit 失效
标题翻译：铁电集成电路制造工艺
公开(公告)号：US5466629A
公开(公告)日：1995-11-14
申请号：US383575
申请日：1995-02-03
申请人： Takashi Mihara , Hiroyuki Yoshimori , Hitoshi Watanabe , Larry D. McMillan , Carlos P. De Araujo
发明人： Takashi Mihara , Hiroyuki Yoshimori , Hitoshi Watanabe , Larry D. McMillan , Carlos P. De Araujo
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10808 , H01L28/60 , H01L28/55
摘要： An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered. In another embodiment both the bottom and top electrode may be made of silicon, silicide, polycide or a conductive oxide, such as indium tin oxide, tin dioxide, or ruthenium oxide.
摘要翻译：超大型铁电电容器位于DRAM中的MOSFET源极/漏极的接触孔处。在铁电层和源极漏极之间，由氮化钛，钛钨，钽，钛，钨，钼，铬，氧化铟锡，二氧化锡，氧化钌，硅，硅化物或多晶硅化物形成的阻挡层。阻挡层可以用作铁电电容器的底部电极，或者可以使用由铂制成的单独的底部电极。在其中阻挡层形成底部电极的另一个实施例中，小于5nm厚的氧化物层位于势垒层和铁电层之间，阻挡层由硅，硅化物或多硅化物制成。薄的硅化物层在阻挡层和源极/漏极之间形成欧姆接触。在单个掩模步骤中对电容器和阻挡层进行图案化。电容器的端部是阶梯式或锥形的。在另一个实施例中，底部和顶部电极可以由硅，硅化物，多晶硅或导电氧化物，例如氧化铟锡，二氧化锡或氧化钌制成。

4. 发明授权

US5434102A Process for fabricating layered superlattice materials and making electronic devices including same 失效
标题翻译：用于制造分层超晶格材料并制造包括其的电子器件的方法
公开(公告)号：US5434102A
公开(公告)日：1995-07-18
申请号：US65656
申请日：1993-05-21
申请人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
发明人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
IPC分类号： B05D1/00 , B05D3/04 , B05D7/24 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C26/02 , C30B7/00 , H01C7/10 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/108 , H01L27/115 , H01L41/24 , H05K3/10 , H01L21/385
CPC分类号： B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1225 , C23C18/1279 , C23C18/1283 , C23C18/1295 , C23C26/02 , C30B29/68 , C30B7/00 , C30B7/005 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L27/11507 , H01L28/56 , H01L28/60 , H01L41/317 , H01L28/55 , H05K3/105
摘要： A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.
摘要翻译：将含有金属的液体前体施加到基材上，进行RTP烘焙并退火以形成层状超晶格材料。除了高铋含量前体之外，预处理RTP和退火中的底物和氧是至关重要的。化学计量的110％至140％之间的过量铋和725℃的RTP温度是最佳的。该膜形成为两层，其中第一层使用化学计量的前体，其中第二层使用过量的铋前体。电子性质如此定期地取决于工艺参数和材料组成，并且这种各种各样的材料是可能的，可以通过从一个或多个电子性质的值的连续记录中选择电子装置作为连续功能工艺参数和材料组成，并利用所选择的工艺和材料组成制造设备。

5. 发明授权

US5439845A Process for fabricating layered superlattice materials and making electronic devices including same 失效
公开(公告)号：US5439845A
公开(公告)日：1995-08-08
申请号：US350323
申请日：1994-12-05
申请人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
发明人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
IPC分类号： B05D1/00 , B05D3/04 , B05D7/24 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C26/02 , C30B7/00 , H01C7/10 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/108 , H01L27/115 , H01L41/24 , H05K3/10 , H01L29/15
CPC分类号： B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1225 , C23C18/1279 , C23C18/1283 , C23C18/1295 , C23C26/02 , C30B29/68 , C30B7/00 , C30B7/005 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L27/11507 , H01L28/56 , H01L28/60 , H01L41/317 , H01L28/55 , H05K3/105
摘要： A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.

6. 发明授权

US5719416A Integrated circuit with layered superlattice material compound 失效
标题翻译：集成电路与层状超晶格材料复合
公开(公告)号：US5719416A
公开(公告)日：1998-02-17
申请号：US276805
申请日：1994-07-18
申请人： Hiroyuki Yoshimori , Hitoshi Watanabe , Carlos A. Paz De Araujo , Shuzo Hiraide , Takashi Mihara , Larry D. McMillan
发明人： Hiroyuki Yoshimori , Hitoshi Watanabe , Carlos A. Paz De Araujo , Shuzo Hiraide , Takashi Mihara , Larry D. McMillan
IPC分类号： C23C18/12 , C30B7/00 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11502 , C23C16/45561 , C30B29/68 , C30B7/00 , H01L21/31691 , H01L27/10805 , H01L28/56 , H01L28/60 , H01L28/55
摘要： A method of fabricating a ferroelectric or layered superlattice DRAM compatible with conventional silicon CMOS technology. A MOSFET is formed on a silicon substrate. A thick layer of BPSG followed by a thin SOG layer overlies the MOSFET. A capacitor is formed by depositing a layer of platinum, annealing, depositing an intermediate layer comprising a ferroelectric or layer superlattice material, annealing, depositing a second layer of platinum, then patterning the capacitor. Another SOG layer is deposited, contact holes to the MOSFET and capacitor are partially opened, the SOG is annealed, the contact holes are completely opened, and a Pt/Ti/PtSi wiring layer is deposited.
摘要翻译：制造与常规硅CMOS技术兼容的铁电或分层超晶格DRAM的方法。在硅衬底上形成MOSFET。厚层的BPSG后面是薄的SOG层覆盖在MOSFET上。通过沉积铂层，退火，沉积包含铁电体或层超晶格材料的中间层，退火，沉积第二层铂，然后构图电容器，形成电容器。沉积另一个SOG层，MOSFET和电容器的接触孔部分打开，SOG退火，接触孔完全打开，并沉积Pt / Ti / PtSi布线层。

7. 发明授权

US5561307A Ferroelectric integrated circuit 失效
标题翻译：铁电集成电路
公开(公告)号：US5561307A
公开(公告)日：1996-10-01
申请号：US276474
申请日：1994-07-18
申请人： Takashi Mihara , Hiroyuki Yoshimori , Hitoshi Watanabe , Larry D. McMillan , Carlos P. De Araujo
发明人： Takashi Mihara , Hiroyuki Yoshimori , Hitoshi Watanabe , Larry D. McMillan , Carlos P. De Araujo
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/76 , C23C14/00 , H01L29/94
CPC分类号： H01L27/10852 , H01L27/10808 , H01L28/60 , H01L28/55
摘要： An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered. In another embodiment both the bottom and top electrode may be made of silicon, silicide, polycide or a conductive oxide, such as indium tin oxide, tin dioxide, or ruthenium oxide.
摘要翻译：超大型铁电电容器位于DRAM中的MOSFET源极/漏极的接触孔处。在铁电层和源极漏极之间，由氮化钛，钛钨，钽，钛，钨，钼，铬，氧化铟锡，二氧化锡，氧化钌，硅，硅化物或多晶硅化物形成的阻挡层。阻挡层可以用作铁电电容器的底部电极，或者可以使用由铂制成的单独的底部电极。在其中阻挡层形成底部电极的另一个实施例中，小于5nm厚的氧化物层位于势垒层和铁电层之间，阻挡层由硅，硅化物或多硅化物制成。薄的硅化物层在阻挡层和源极/漏极之间形成欧姆接触。在单个掩模步骤中对电容器和阻挡层进行图案化。电容器的端部是阶梯式或锥形的。在另一个实施例中，底部和顶部电极可以由硅，硅化物，多晶硅或导电氧化物，例如氧化铟锡，二氧化锡或氧化钌制成。

8. 发明授权

US5487032A Method and apparatus for reduced fatigue in ferroelectric memory elements 失效
标题翻译：铁电存储元件疲劳减少的方法和装置
公开(公告)号：US5487032A
公开(公告)日：1996-01-23
申请号：US338003
申请日：1994-11-10
申请人： Takashi Mihara , Hitoshi Watanabe , Hiroyuki Yoshimori , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Takashi Mihara , Hitoshi Watanabe , Hiroyuki Yoshimori , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A method and apparatus for programming ferroelectric memory cells which reduces fatigue effects of switching polarization of the ferroelectric devices associated with the memory cells such as ferroelectric capacitors and transistors. Alteration of the rise AC fall times associated with signals used to switch ferroelectric device polarization are shown to reduce fatigue of the ferroelectric material thereby increasing the useful life of ferroelectric memory cells. Slowing the rise and fall times as well as the rate of signal level rise and fall, (signal shape), are shown to reduce the fatigue effects of switching polarization of ferroelectric devices. Methods and apparatus for producing a triangular ("sawtooth") signal waveform, a Gaussian signal waveform, and a waveform having exponential rise and fall times are disclosed.
摘要翻译：一种用于编程铁电存储器单元的方法和装置，其减少与诸如铁电电容器和晶体管之类的存储单元相关联的铁电体器件的开关极化的疲劳效应。示出了与用于切换铁电体器件极化的信号相关联的上升AC下降时间的变化，以减少铁电材料的疲劳，从而增加铁电存储器单元的使用寿命。降低上升和下降时间以及信号电平上升和下降（信号形状）的速率，可以减少铁电元件开关极化的疲劳效应。公开了用于产生三角形（“锯齿”）信号波形，高斯信号波形和具有指数上升和下降时间的波形的方法和装置。

9. 发明授权

US5825057A Process for fabricating layered superlattice materials and making electronic devices including same 失效
公开(公告)号：US5825057A
公开(公告)日：1998-10-20
申请号：US349692
申请日：1994-12-05
申请人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
发明人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
IPC分类号： B05D1/00 , B05D3/04 , B05D7/24 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C26/02 , C30B7/00 , H01C7/10 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/108 , H01L27/115 , H01L41/24 , H05K3/10 , H01L29/76
CPC分类号： B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1225 , C23C18/1279 , C23C18/1283 , C23C18/1295 , C23C26/02 , C30B29/68 , C30B7/00 , C30B7/005 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L27/11507 , H01L28/56 , H01L28/60 , H01L41/317 , H01L28/55 , H05K3/105
摘要： A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.

10. 发明授权

US5468684A Integrated circuit with layered superlattice material and method of fabricating same 失效
标题翻译：具有分层超晶格材料的集成电路及其制造方法
公开(公告)号：US5468684A
公开(公告)日：1995-11-21
申请号：US65666
申请日：1993-05-21
申请人： Hiroyuki Yoshimori , Hitoshi Watanabe , Carlos A. Paz De Araujo , Shuzo Hiraide , Takashi Mihara , Larry D. McMillan
发明人： Hiroyuki Yoshimori , Hitoshi Watanabe , Carlos A. Paz De Araujo , Shuzo Hiraide , Takashi Mihara , Larry D. McMillan
IPC分类号： C23C16/02 , C23C16/40 , C23C16/56 , C23C18/12 , C30B7/00 , C30B25/02 , H01C7/10 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/108 , H01L27/115 , H01L21/465
CPC分类号： C23C16/0218 , B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/40 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C16/56 , C23C18/1216 , C23C18/1225 , C23C26/02 , C30B25/02 , C30B29/68 , C30B7/00 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/56 , H01L28/60 , H01L41/317 , H01L28/55 , H01L41/187 , H05K3/105
摘要： A method of fabricating a ferroelectric or layered superlattice DRAM compatible with conventional silicon CMOS technology. A MOSFET is formed on a silicon substrate. A thick layer of BPSG followed by a thin SOG layer overlies the MOSFET. A capacitor is formed by depositing a layer of platinum, annealing, depositing an intermediate layer comprising a ferroelectric or layered superlattice material, annealing, depositing a second layer of platinum, then patterning the capacitor. Another SOG layer is deposited, contact holes to the MOSFET and capacitor are partially opened, the SOG is annealed, the contact holes are completely opened, and a Pt/Ti/PtSi wiring layer is deposited.
摘要翻译：制造与常规硅CMOS技术兼容的铁电或分层超晶格DRAM的方法。在硅衬底上形成MOSFET。厚层的BPSG后面是薄的SOG层覆盖在MOSFET上。通过沉积铂层，退火，沉积包含铁电或层状超晶格材料的中间层，退火，沉积第二层铂，然后构图电容器，形成电容器。沉积另一个SOG层，MOSFET和电容器的接触孔部分打开，SOG退火，接触孔完全打开，并沉积Pt / Ti / PtSi布线层。

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