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1. 发明申请

US20110024825A1 SEMICONDUCTOR MEMORY 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20110024825A1
公开(公告)日：2011-02-03
申请号：US12898914
申请日：2010-10-06
申请人： Tatsuo Izumi , Takeshi Kamigaichi , Shinya Takahashi
发明人： Tatsuo Izumi , Takeshi Kamigaichi , Shinya Takahashi
IPC分类号： H01L29/792
CPC分类号： H01L27/105 , H01L27/0207 , H01L27/11526 , H01L27/11534 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction.
摘要翻译：根据本发明的示例的半导体存储器包括有源区域和隔离有源区域的元件隔离区域。有源区域和元件隔离区域沿第一方向交替布置。从第一方向最端部分的第n（n是奇数）有效区域和第（n + 1）有效区域在垂直于第一方向的第二方向上的最末端处彼此耦合。

2. 发明授权

US07825439B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07825439B2
公开(公告)日：2010-11-02
申请号：US12191592
申请日：2008-08-14
申请人： Tatsuo Izumi , Takeshi Kamigaichi , Shinya Takahashi
发明人： Tatsuo Izumi , Takeshi Kamigaichi , Shinya Takahashi
IPC分类号： H01L29/768
CPC分类号： H01L27/105 , H01L27/0207 , H01L27/11526 , H01L27/11534 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction.
摘要翻译：根据本发明的示例的半导体存储器包括有源区域和隔离有源区域的元件隔离区域。有源区域和元件隔离区域沿第一方向交替布置。从第一方向最端部分的第n（n是奇数）有效区域和第（n + 1）有效区域在垂直于第一方向的第二方向上的最末端处彼此耦合。

3. 发明授权

US08497543B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08497543B2
公开(公告)日：2013-07-30
申请号：US13234260
申请日：2011-09-16
申请人： Jun Ogi , Takeshi Kamigaichi , Tatsuo Izumi
发明人： Jun Ogi , Takeshi Kamigaichi , Tatsuo Izumi
IPC分类号： H01L29/76
CPC分类号： H01L27/11524 , H01L21/76229 , H01L21/7682
摘要： A semiconductor memory device includes a semiconductor substrate, a plurality of element isolations, a plurality of first stacked bodies, a second stacked body, and an interlayer insulating film. Distance between each of the first stacked bodies and the second stacked body is longer than distance between adjacent ones of the first stacked bodies. A first void is formed in the interlayer insulating film between the first stacked bodies. A second void is formed in the interlayer insulating film between one of the first stacked bodies and the second stacked body. And, a lower end of the second void is located above a lower end of the first void.
摘要翻译：半导体存储器件包括半导体衬底，多个元件隔离，多个第一层叠体，第二层叠体和层间绝缘膜。第一层叠体和第二层叠体之间的距离比相邻的第一层叠体的距离长。在第一堆叠体之间的层间绝缘膜中形成第一空隙。在第一层叠体和第二层叠体之间的层间绝缘膜中形成第二空隙。并且，第二空隙的下端位于第一空隙的下端之上。

4. 发明授权

US07800163B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07800163B2
公开(公告)日：2010-09-21
申请号：US12245199
申请日：2008-10-03
申请人： Tatsuo Izumi , Takeshi Kamigaichi
发明人： Tatsuo Izumi , Takeshi Kamigaichi
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.
摘要翻译：非易失性半导体存储装置包括：基板; 设置在所述基板上的控制电路层; 设置在所述控制电路层上的支撑层; 以及设置在支撑层上的存储单元阵列层。存储单元阵列层包括：第一层叠部分，其具有交替层叠在其中的第一绝缘层和第一导电层; 以及设置在相应的第一层叠部分的顶表面或底表面上并层压以在第二绝缘层之间形成第二导电层的第二层压部件。所述控制电路层包括以下中的至少一个：行解码器驱动设置在所述存储单元阵列层中的字线，以及读出放大器，用于感测和放大来自设置在所述存储单元阵列层中的位线的信号。

5. 发明申请

US20110141821A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20110141821A1
公开(公告)日：2011-06-16
申请号：US13034309
申请日：2011-02-24
申请人： Tatsuo IZUMI , Takeshi Kamigaichi
发明人： Tatsuo IZUMI , Takeshi Kamigaichi
IPC分类号： G11C16/08 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.
摘要翻译：非易失性半导体存储装置包括：基板; 设置在所述基板上的控制电路层; 设置在所述控制电路层上的支撑层; 以及设置在支撑层上的存储单元阵列层。存储单元阵列层包括：第一层叠部分，其具有交替层叠在其中的第一绝缘层和第一导电层; 以及设置在相应的第一层叠部分的顶表面或底表面上并层压以在第二绝缘层之间形成第二导电层的第二层压部件。所述控制电路层包括以下中的至少一个：行解码器驱动设置在所述存储单元阵列层中的字线，以及读出放大器，用于感测和放大来自设置在所述存储单元阵列层中的位线的信号。

6. 发明授权

US07902023B2 Method of manufacturing non-volatile semiconductor storage device 有权
标题翻译：制造非易失性半导体存储装置的方法
公开(公告)号：US07902023B2
公开(公告)日：2011-03-08
申请号：US12858478
申请日：2010-08-18
申请人： Tatsuo Izumi , Takeshi Kamigaichi
发明人： Tatsuo Izumi , Takeshi Kamigaichi
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.
摘要翻译：非易失性半导体存储装置包括：基板; 设置在所述基板上的控制电路层; 设置在所述控制电路层上的支撑层; 以及设置在支撑层上的存储单元阵列层。存储单元阵列层包括：第一层叠部分，其具有交替层叠在其中的第一绝缘层和第一导电层; 以及设置在相应的第一层叠部分的顶表面或底表面上并层压以在第二绝缘层之间形成第二导电层的第二层压部件。所述控制电路层包括以下中的至少一个：行解码器驱动设置在所述存储单元阵列层中的字线，以及读出放大器，用于感测和放大来自设置在所述存储单元阵列层中的位线的信号。

7. 发明申请

US20090090960A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20090090960A1
公开(公告)日：2009-04-09
申请号：US12245199
申请日：2008-10-03
申请人： Tatsuo IZUMI , Takeshi Kamigaichi
发明人： Tatsuo IZUMI , Takeshi Kamigaichi
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.
摘要翻译：非易失性半导体存储装置包括：基板; 设置在所述基板上的控制电路层; 设置在所述控制电路层上的支撑层; 以及设置在支撑层上的存储单元阵列层。存储单元阵列层包括：第一层叠部分，其具有交替层叠在其中的第一绝缘层和第一导电层; 以及设置在相应的第一层叠部分的顶表面或底表面上并层压以在第二绝缘层之间形成第二导电层的第二层压部件。所述控制电路层包括以下中的至少一个：行解码器驱动设置在所述存储单元阵列层中的字线，以及读出放大器，用于感测和放大来自设置在所述存储单元阵列层中的位线的信号。

8. 发明授权

US08324680B2 Non-volatile semiconductor storage device with laminated vertical memory cell and select transistors 有权
标题翻译：具有层叠垂直存储单元和选择晶体管的非易失性半导体存储器件
公开(公告)号：US08324680B2
公开(公告)日：2012-12-04
申请号：US13034309
申请日：2011-02-24
申请人： Tatsuo Izumi , Takeshi Kamigaichi
发明人： Tatsuo Izumi , Takeshi Kamigaichi
IPC分类号： H01L29/792 , G11C16/08
CPC分类号： H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.
摘要翻译：非易失性半导体存储装置包括：基板; 设置在所述基板上的控制电路层; 设置在所述控制电路层上的支撑层; 以及设置在支撑层上的存储单元阵列层。存储单元阵列层包括：第一层叠部分，其具有交替层叠在其中的第一绝缘层和第一导电层; 以及设置在相应的第一层叠部分的顶表面或底表面上并层压以在第二绝缘层之间形成第二导电层的第二层压部件。所述控制电路层包括以下中的至少一个：行解码器驱动设置在所述存储单元阵列层中的字线，以及读出放大器，用于感测和放大来自设置在所述存储单元阵列层中的位线的信号。

9. 发明申请

US20120241910A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120241910A1
公开(公告)日：2012-09-27
申请号：US13234260
申请日：2011-09-16
申请人： Jun OGI , Takeshi Kamigaichi , Tatsuo Izumi
发明人： Jun OGI , Takeshi Kamigaichi , Tatsuo Izumi
IPC分类号： H01L29/06 , H01L21/31
CPC分类号： H01L27/11524 , H01L21/76229 , H01L21/7682
摘要： A semiconductor memory device includes a semiconductor substrate, a plurality of element isolations, a plurality of first stacked bodies, a second stacked body, and an interlayer insulating film. Distance between each of the first stacked bodies and the second stacked body is longer than distance between adjacent ones of the first stacked bodies. A first void is formed in the interlayer insulating film between the first stacked bodies. A second void is formed in the interlayer insulating film between one of the first stacked bodies and the second stacked body. And, a lower end of the second void is located above a lower end of the first void.
摘要翻译：半导体存储器件包括半导体衬底，多个元件隔离，多个第一层叠体，第二层叠体和层间绝缘膜。第一层叠体和第二层叠体之间的距离比相邻的第一层叠体的距离长。在第一堆叠体之间的层间绝缘膜中形成第一空隙。在第一层叠体和第二层叠体之间的层间绝缘膜中形成第二空隙。并且，第二空隙的下端位于第一空隙的下端之上。

10. 发明授权

US08270212B2 Semiconductor memory device including alternately arranged contact members 有权
标题翻译：半导体存储器件包括交替布置的接触构件
公开(公告)号：US08270212B2
公开(公告)日：2012-09-18
申请号：US12910674
申请日：2010-10-22
申请人： Tatsuo Izumi , Takeshi Kamigaichi
发明人： Tatsuo Izumi , Takeshi Kamigaichi
IPC分类号： G11C11/15
CPC分类号： G11C16/0483 , H01L23/5226 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor memory device includes first and second upper-layer contact members. The upper-layer contact members are arranged alternately with the first upper-layer contact members in a first direction and shifted in a second direction orthogonal to the first direction. Plugs are formed on the second upper-layer contact members. First metal wirings are provided on the first upper-layer contact members. Second metal wirings are provided on the plugs. A height of a top surface of the plugs is higher than a top surface of the first metal wirings. A width of a bottom surface of the first metal wirings in a shorter-side direction is shorter than a width of a top surface of the first metal wirings. A width of a bottom surface of the second metal wirings in a shorter-side direction is shorter than a width of a top surface of the second metal wirings.
摘要翻译：根据一个实施例，半导体存储器件包括第一和第二上层接触构件。上层接触构件与第一上层接触构件沿第一方向交替布置，并且沿与第一方向正交的第二方向移位。插塞形成在第二上层接触构件上。第一金属配线设置在第一上层接触构件上。插头上设有第二金属布线。插头顶表面的高度高于第一金属布线的顶表面。第一金属配线在短边方向上的底面的宽度比第一金属布线的顶面的宽度短。第二金属配线在短边方向上的底面的宽度比第二金属配线的上表面的宽度短。

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