专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06826167B2 Mobile communication system 失效
标题翻译：移动通信系统
公开(公告)号：US06826167B2
公开(公告)日：2004-11-30
申请号：US09919913
申请日：2001-08-02
申请人： Tatsuaki Osafune , Katsuyoshi Kitai , Tohru Hoshi , Tomohiro Hotta , Koji Hirayama
发明人： Tatsuaki Osafune , Katsuyoshi Kitai , Tohru Hoshi , Tomohiro Hotta , Koji Hirayama
IPC分类号： H04Q728
CPC分类号： H04W76/14 , H04W92/02
摘要： A communication relay system is connected to a line switched mobile communication system adapted to accommodate therein mobile terminals through radio channels and a packet switched mobile communication system adapted to accommodate therein the mobile terminals through radio channels. When a connection request has been made to a portable terminal, the communication relay system judges whether the portable terminal of interest is connected either to the line switched mobile communication system or to the packet switched mobile communication system.
摘要翻译：通信中继系统连接到适于通过无线电信道容纳移动终端的线路交换移动通信系统和适于通过无线电信道在其中容纳移动终端的分组交换移动通信系统。当对便携式终端进行连接请求时，通信中继系统判断感兴趣的便携式终端是连接到线路交换移动通信系统还是与分组交换的移动通信系统连接。

2. 发明授权

US6112248A Method and system for dynamically balancing network traffic using address resolution protocol 失效
标题翻译：使用地址解析协议动态平衡网络流量的方法和系统
公开(公告)号：US6112248A
公开(公告)日：2000-08-29
申请号：US18564
申请日：1998-02-04
申请人： Frederico Buchholz Maciel , Katsuyoshi Kitai , Satoshi Yoshizawa , Hideki Murahashi , Tatsuo Higuchi
发明人： Frederico Buchholz Maciel , Katsuyoshi Kitai , Satoshi Yoshizawa , Hideki Murahashi , Tatsuo Higuchi
IPC分类号： H04L12/751 , H04L12/803 , H04L29/06 , H04L29/08 , H04L29/12 , H04L29/14 , G06F15/173
CPC分类号： H04L45/00 , H04L29/12009 , H04L29/12018 , H04L45/04 , H04L45/12 , H04L45/24 , H04L61/10 , H04L67/1002 , H04L67/101 , H04L67/1036 , H04L67/42 , H04L69/40
摘要： This invention provides dynamic balance of the traffic among data processing devices interconnecting networks and thereby improve the networking performance. For network traffic flowing between a first network and a second network, the traffic is distributed among the data processing devices that act as routers according to the traffic amount. An algorithm for balancing the traffic is used to select appropriate data processing devices as routers.
摘要翻译：本发明提供了互连网络的数据处理设备之间的流量的动态平衡，从而提高了网络性能。对于在第一网络和第二网络之间流动的网络流量，流量根据流量量分配在充当路由器的数据处理设备之间。用于平衡流量的算法用于选择适当的数据处理设备作为路由器。

3. 发明授权

US5903724A Method of transferring packet data in a network by transmitting divided data packets 失效
标题翻译：通过发送划分的数据包在网络中传送分组数据的方法
公开(公告)号：US5903724A
公开(公告)日：1999-05-11
申请号：US708955
申请日：1996-09-06
申请人： Yoshifumi Takamoto , Hiroki Kanai , Tadahiro Takase , Katsuyoshi Kitai , Yoshimasa Masuoka
发明人： Yoshifumi Takamoto , Hiroki Kanai , Tadahiro Takase , Katsuyoshi Kitai , Yoshimasa Masuoka
IPC分类号： G06F13/00 , H04L1/16 , H04L1/18 , H04L12/70 , H04L29/06 , H04L29/08 , G06F3/00
CPC分类号： H04L29/06 , H04L1/1809 , H04L1/16 , H04L1/1874 , H04L69/324
摘要： A communication controller at the sending computer divides data transferred from a host into sub-ACK unit packets and transfers them sequentially to a destination without waiting for the sub-ACK's being subsequently provided by the destination. A communication controller at the receiving computer issues a sub-ACK to the sending computer for each of the sub-ACK unit packet, if the sub-ACK packet has been normally received and otherwise issues retransmission request for the sub-ACK unit packets and merges data included in the sub-ACK unit packets into the initial data, after they are normally received.
摘要翻译：发送计算机上的通信控制器将从主机传送的数据分割为子ACK单元分组，并将它们顺序地传送到目的地，而不必等待目的地随后提供的副ACK。如果副ACK分组已被正常接收，则在接收计算机上的通信控制器向发送计算机发送子ACK，以便对于每个子ACK单元分组发送子ACK，并且另外发出用于子ACK单元分组的重发请求并合并包含在子ACK单元中的数据在它们被正常接收之后被分组成初始数据。

4. 发明授权

US5432920A Store control method with hierarchic priority scheme for computer system 失效
标题翻译：存储控制方法与计算机系统的层次优先级方案
公开(公告)号：US5432920A
公开(公告)日：1995-07-11
申请号：US685450
申请日：1991-04-15
申请人： Shigeko Yazawa , Tadaaki Isobe , Mihoko Hashiba , Katsuyoshi Kitai
发明人： Shigeko Yazawa , Tadaaki Isobe , Mihoko Hashiba , Katsuyoshi Kitai
IPC分类号： G06F13/18 , G06F13/16
CPC分类号： G06F13/18
摘要： A store control method for a computer system having a storage with independently accessible plural store banks, plural access request controllers for issuing access requests to the storage, and a store controller for transmitting the access requests to each store bank. The store controller has an access request priority determining circuit of plural stages for selecting the access requests in the order of higher priority for each store bank so as to determine the order of priority between the access requests in multiple stages on the basis of the access requests. Further, plural priority control circuits of each stage are provided for stepwise performing control of priority of the main store access requests issued by the vector data processor for each of the store banks. Access is made to the main storage by assuring the order between the vector elements constituting vector data by allowing each first priority control circuit to send the access requests to the priority control circuit of next stage. Furthermore, the priority control circuit of the n-th stage sends the access request from the plural priority control circuits of the (n-1)th stage while assuring the order of the priority control circuits of the (n- 1)th stage.
摘要翻译：一种用于具有可独立存取的多个存储库的存储器的计算机系统的存储控制方法，用于向存储器发出访问请求的多个访问请求控制器，以及用于将访问请求发送到每个存储库的存储控制器。存储控制器具有多级的访问请求优先级确定电路，用于以每个存储库的更高优先级的顺序选择访问请求，以便基于访问请求确定多级的访问请求之间的优先级顺序。此外，提供每级的多个优先级控制电路，用于逐步执行由矢量数据处理器针对每个商店银行发出的主存储访问请求的优先级的控制。通过允许每个第一优先级控制电路将访问请求发送到下一级的优先级控制电路，通过确保构成向量数据的向量元素之间的顺序来访问主存储器。此外，第n级的优先级控制电路在确保第（n-1）级的优先级控制电路的顺序的同时，从第（n-1）级的多个优先级控制电路发送访问请求。

5. 发明授权

US06404766B1 Network data communication system 失效
标题翻译：网络数据通信系统
公开(公告)号：US06404766B1
公开(公告)日：2002-06-11
申请号：US08773315
申请日：1996-12-24
申请人： Katsuyoshi Kitai , Yoshimasa Masuoka , Satoshi Yoshizawa , Frederico Buchholz Maciel , Toshiaki Tarui , Tatsuo Higuchi , Hideki Murahashi
发明人： Katsuyoshi Kitai , Yoshimasa Masuoka , Satoshi Yoshizawa , Frederico Buchholz Maciel , Toshiaki Tarui , Tatsuo Higuchi , Hideki Murahashi
IPC分类号： H04L1256
CPC分类号： H04W80/06 , H04L12/2856 , H04L12/2874 , H04L12/5691 , H04L12/66 , H04L29/06 , H04L29/12009 , H04L29/12367 , H04L29/12377 , H04L29/12509 , H04L29/12924 , H04L61/2514 , H04L61/2517 , H04L61/2567 , H04L61/6063 , H04L69/16 , H04L69/163
摘要： In order to execute a flow control and a congestion control in a hop-by-hop manner in a data communication among computers connected to different networks, in a data communication between a client A1 and a remote server B, a communication proxy of the remote server B is located in a local server A in an LAN to which the client A belongs. A communication packet to be routed to the remote server B is stolen (received) and passed to a transport layer. A TCP communication between the client A1 and the remote server B is divided into two; a communication between the client A1 and the communication proxy of the remote server B and a communication between the communication proxy of the remote server B and the remote server B.
摘要翻译：为了在连接到不同网络的计算机之间的数据通信中以逐跳的方式执行流量控制和拥塞控制，在客户机A1和远程服务器B之间的数据通信中，遥控器的通信代理服务器B位于客户端A所属的LAN中的本地服务器A中。要路由到远程服务器B的通信分组被盗（接收）并被传送到传输层。客户端A1和远程服务器B之间的TCP通信被分成两部分; 客户端A1和远程服务器B的通信代理之间的通信以及远程服务器B的通信代理和远程服务器B之间的通信。

6. 发明授权

US5948069A Networking system and parallel networking method 失效
标题翻译：网络系统和并行网络方式
公开(公告)号：US5948069A
公开(公告)日：1999-09-07
申请号：US684572
申请日：1996-07-19
申请人： Katsuyoshi Kitai , Satoshi Yoshizawa , Toyohiko Kagimasa , Fumio Noda , Yoshimasa Masuoka , Yoshifumi Takamoto
发明人： Katsuyoshi Kitai , Satoshi Yoshizawa , Toyohiko Kagimasa , Fumio Noda , Yoshimasa Masuoka , Yoshifumi Takamoto
IPC分类号： G06F13/00 , H04L29/04 , H04L29/06 , G06F13/38 , G06F15/17
CPC分类号： H04L29/06 , H04L45/745 , H04L49/351 , H04L49/205 , H04L49/3009 , H04L67/42
摘要： A networking method and system for performing data communication to a client computer from a server computer having a plurality of network interfaces through a network. The invention includes a LAN switch, provided between the network and the server computer. The LAN switch includes a plurality of communication paths correspondingly connected to the network interfaces of the server computer. Any one of the communication paths are usable to connect the client computer with the server computer. The invention further includes a selector for selecting one of the communication paths in accordance with a quality of service (QOS) requested by the client computer. The selector selects the communication path using information contained in a routing table in the server computer based on a network address of the network connected to the client computer. The routing table includes the address of the network connected to the client computer and addresses of network interfaces of the server computer correspondingly connected to the communication path.
摘要翻译：一种用于通过网络从具有多个网络接口的服务器计算机向客户端计算机执行数据通信的联网方法和系统。本发明包括在网络和服务器计算机之间提供的LAN交换机。 LAN交换机包括相应地连接到服务器计算机的网络接口的多个通信路径。任何一个通信路径都可用于将客户端计算机与服务器计算机连接起来。本发明还包括一个选择器，用于根据客户计算机请求的服务质量（QOS）来选择一个通信路径。选择器根据连接到客户端计算机的网络的网络地址，使用包含在服务器计算机中的路由表中的信息来选择通信路径。路由表包括连接到客户端计算机的网络的地址以及与通信路径相对应的服务器计算机的网络接口的地址。

7. 发明授权

US5857110A Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors 失效
标题翻译：优先级控制，并行切换向量处理器的优先级，用于矢量处理器共享的存储器模块的多个优先级电路
公开(公告)号：US5857110A
公开(公告)日：1999-01-05
申请号：US760525
申请日：1996-12-05
申请人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F13/18 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027 , G06F13/18
摘要： In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
摘要翻译：在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。为存储控制单元中包含的优先级电路提供优先级位信息。在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为生成的优先级控制电路和所有优先级电路之间。

8. 发明授权

US5396603A Data processor having resources and execution start control for starting execution of succeeding instruction in resource before completion of preceding instruction 失效
标题翻译：数据处理器具有资源和执行开始控制，用于在完成前一指令之前开始执行资源中的后续指令
公开(公告)号：US5396603A
公开(公告)日：1995-03-07
申请号：US634810
申请日：1990-12-31
申请人： Yoshiko Tamaki , Shigeko Yazawa , Yasuhiro Inagami , Katsuyoshi Kitai
发明人： Yoshiko Tamaki , Shigeko Yazawa , Yasuhiro Inagami , Katsuyoshi Kitai
IPC分类号： G06F9/38 , G06F15/78 , G06F17/16
CPC分类号： G06F9/3836 , G06F15/8084 , G06F9/3857 , G06F9/3867
摘要： A data processor having memory requesters to execute instructions, an instruction hold unit disposed for each resource to hold an instruction being executed in the resource and instructions to be executed therein, and execution control units to cause, in a case where an execution completion report of an instruction being executed in either one of the resources is received, an instruction held in an instruction hold unit corresponding to the resource to be immediately executed, thereby successively supplying the respective resources with data items to be employed for executions of the consecutive instructions in the resources.
摘要翻译：一种具有用于执行指令的存储器请求器的数据处理器，为每个资源设置的指令保持单元，用于保存正在该资源中执行的指令以及要在其中执行的指令;以及执行控制单元，其在执行完成报告在任一资源中执行的指令被接收，指令保持单元中保持的指令与要立即执行的资源相对应，从而向相应资源依次提供要用于执行连续指令的数据项资源。

9. 发明授权

US06330604B1 Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage 失效
标题翻译：独占控制方法，每个节点控制对共享资源的专用使用请求的问题，其计算机系统和具有用于检测将事件标志写入共享主存储器的电路的计算机系统
公开(公告)号：US06330604B1
公开(公告)日：2001-12-11
申请号：US09102812
申请日：1998-06-23
申请人： Tatsuo Higuchi , Toshiaki Tarui , Katsuyoshi Kitai , Shigeo Takeuchi , Tatsuru Toba , Machiko Asaie , Yasuhiro Inagami
发明人： Tatsuo Higuchi , Toshiaki Tarui , Katsuyoshi Kitai , Shigeo Takeuchi , Tatsuru Toba , Machiko Asaie , Yasuhiro Inagami
IPC分类号： G06F15167
CPC分类号： G06F9/52 , G06F15/17381 , H04L45/06
摘要： A computer system including a plurality of processing nodes, at least one resource provided for use by any of the processing nodes and a plurality of register sets. Each register set is provided in each of the processing nodes for storing in parallel use status information indicating whether the resource is in exclusive use status or not. The computer system can also include a plurality of request issue circuits, each being provided in each of the processing nodes, for issuing individually requests for exclusive use of the resource, a message exchanging circuit for serializing requests issued by the request issue circuits into a serialized order and broadcasting the request to all of the processing nodes in the serialized order and a plurality of status control circuits. Each status control circuit is provided in each of the processing nodes corresponding to each of the register sets to update individually a corresponding register set depending on use status information stored in the corresponding register set and each of the requests for exclusive use of the resource received at a corresponding node.
摘要翻译：一种包括多个处理节点的计算机系统，提供给任何处理节点使用的至少一个资源和多个寄存器组。在每个处理节点中提供每个寄存器组，用于并行地存储指示资源是否处于独占状态的状态信息。计算机系统还可以包括多个请求发布电路，每个请求发布电路分别设置在每个处理节点中，用于单独发出专用于资源的请求;消息交换电路，用于将请求发布电路发出的请求串行化为串行化以序列顺序向多个处理节点发送请求并将其发送给多个状态控制电路。每个状态控制电路被提供在与每个寄存器组相对应的每个处理节点中，以根据存储在相应寄存器组中的使用状态信息单独地更新对应的寄存器组，并且每个对专用的资源请求相应的节点。

10. 发明授权

US5617575A Interprocessor priority control system for multivector processor 失效
标题翻译：多处理器处理器优先级控制系统
公开(公告)号：US5617575A
公开(公告)日：1997-04-01
申请号：US170743
申请日：1993-12-21
申请人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F13/18 , G06F13/40 , G06F12/00 , G06F15/16
CPC分类号： G06F13/4027 , G06F13/18
摘要： In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
摘要翻译：在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。为存储控制单元中包含的优先级电路提供优先级位信息。在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为生成的优先级控制电路和所有优先级电路之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式