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1. 发明授权

US6112248A Method and system for dynamically balancing network traffic using address resolution protocol 失效
标题翻译：使用地址解析协议动态平衡网络流量的方法和系统
公开(公告)号：US6112248A
公开(公告)日：2000-08-29
申请号：US18564
申请日：1998-02-04
申请人： Frederico Buchholz Maciel , Katsuyoshi Kitai , Satoshi Yoshizawa , Hideki Murahashi , Tatsuo Higuchi
发明人： Frederico Buchholz Maciel , Katsuyoshi Kitai , Satoshi Yoshizawa , Hideki Murahashi , Tatsuo Higuchi
IPC分类号： H04L12/751 , H04L12/803 , H04L29/06 , H04L29/08 , H04L29/12 , H04L29/14 , G06F15/173
CPC分类号： H04L45/00 , H04L29/12009 , H04L29/12018 , H04L45/04 , H04L45/12 , H04L45/24 , H04L61/10 , H04L67/1002 , H04L67/101 , H04L67/1036 , H04L67/42 , H04L69/40
摘要： This invention provides dynamic balance of the traffic among data processing devices interconnecting networks and thereby improve the networking performance. For network traffic flowing between a first network and a second network, the traffic is distributed among the data processing devices that act as routers according to the traffic amount. An algorithm for balancing the traffic is used to select appropriate data processing devices as routers.
摘要翻译：本发明提供了互连网络的数据处理设备之间的流量的动态平衡，从而提高了网络性能。对于在第一网络和第二网络之间流动的网络流量，流量根据流量量分配在充当路由器的数据处理设备之间。用于平衡流量的算法用于选择适当的数据处理设备作为路由器。

2. 发明授权

US5903724A Method of transferring packet data in a network by transmitting divided data packets 失效
标题翻译：通过发送划分的数据包在网络中传送分组数据的方法
公开(公告)号：US5903724A
公开(公告)日：1999-05-11
申请号：US708955
申请日：1996-09-06
申请人： Yoshifumi Takamoto , Hiroki Kanai , Tadahiro Takase , Katsuyoshi Kitai , Yoshimasa Masuoka
发明人： Yoshifumi Takamoto , Hiroki Kanai , Tadahiro Takase , Katsuyoshi Kitai , Yoshimasa Masuoka
IPC分类号： G06F13/00 , H04L1/16 , H04L1/18 , H04L12/70 , H04L29/06 , H04L29/08 , G06F3/00
CPC分类号： H04L29/06 , H04L1/1809 , H04L1/16 , H04L1/1874 , H04L69/324
摘要： A communication controller at the sending computer divides data transferred from a host into sub-ACK unit packets and transfers them sequentially to a destination without waiting for the sub-ACK's being subsequently provided by the destination. A communication controller at the receiving computer issues a sub-ACK to the sending computer for each of the sub-ACK unit packet, if the sub-ACK packet has been normally received and otherwise issues retransmission request for the sub-ACK unit packets and merges data included in the sub-ACK unit packets into the initial data, after they are normally received.
摘要翻译：发送计算机上的通信控制器将从主机传送的数据分割为子ACK单元分组，并将它们顺序地传送到目的地，而不必等待目的地随后提供的副ACK。如果副ACK分组已被正常接收，则在接收计算机上的通信控制器向发送计算机发送子ACK，以便对于每个子ACK单元分组发送子ACK，并且另外发出用于子ACK单元分组的重发请求并合并包含在子ACK单元中的数据在它们被正常接收之后被分组成初始数据。

3. 发明授权

US5432920A Store control method with hierarchic priority scheme for computer system 失效
标题翻译：存储控制方法与计算机系统的层次优先级方案
公开(公告)号：US5432920A
公开(公告)日：1995-07-11
申请号：US685450
申请日：1991-04-15
申请人： Shigeko Yazawa , Tadaaki Isobe , Mihoko Hashiba , Katsuyoshi Kitai
发明人： Shigeko Yazawa , Tadaaki Isobe , Mihoko Hashiba , Katsuyoshi Kitai
IPC分类号： G06F13/18 , G06F13/16
CPC分类号： G06F13/18
摘要： A store control method for a computer system having a storage with independently accessible plural store banks, plural access request controllers for issuing access requests to the storage, and a store controller for transmitting the access requests to each store bank. The store controller has an access request priority determining circuit of plural stages for selecting the access requests in the order of higher priority for each store bank so as to determine the order of priority between the access requests in multiple stages on the basis of the access requests. Further, plural priority control circuits of each stage are provided for stepwise performing control of priority of the main store access requests issued by the vector data processor for each of the store banks. Access is made to the main storage by assuring the order between the vector elements constituting vector data by allowing each first priority control circuit to send the access requests to the priority control circuit of next stage. Furthermore, the priority control circuit of the n-th stage sends the access request from the plural priority control circuits of the (n-1)th stage while assuring the order of the priority control circuits of the (n- 1)th stage.
摘要翻译：一种用于具有可独立存取的多个存储库的存储器的计算机系统的存储控制方法，用于向存储器发出访问请求的多个访问请求控制器，以及用于将访问请求发送到每个存储库的存储控制器。存储控制器具有多级的访问请求优先级确定电路，用于以每个存储库的更高优先级的顺序选择访问请求，以便基于访问请求确定多级的访问请求之间的优先级顺序。此外，提供每级的多个优先级控制电路，用于逐步执行由矢量数据处理器针对每个商店银行发出的主存储访问请求的优先级的控制。通过允许每个第一优先级控制电路将访问请求发送到下一级的优先级控制电路，通过确保构成向量数据的向量元素之间的顺序来访问主存储器。此外，第n级的优先级控制电路在确保第（n-1）级的优先级控制电路的顺序的同时，从第（n-1）级的多个优先级控制电路发送访问请求。

4. 发明授权

US06330604B1 Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage 失效
标题翻译：独占控制方法，每个节点控制对共享资源的专用使用请求的问题，其计算机系统和具有用于检测将事件标志写入共享主存储器的电路的计算机系统
公开(公告)号：US06330604B1
公开(公告)日：2001-12-11
申请号：US09102812
申请日：1998-06-23
申请人： Tatsuo Higuchi , Toshiaki Tarui , Katsuyoshi Kitai , Shigeo Takeuchi , Tatsuru Toba , Machiko Asaie , Yasuhiro Inagami
发明人： Tatsuo Higuchi , Toshiaki Tarui , Katsuyoshi Kitai , Shigeo Takeuchi , Tatsuru Toba , Machiko Asaie , Yasuhiro Inagami
IPC分类号： G06F15167
CPC分类号： G06F9/52 , G06F15/17381 , H04L45/06
摘要： A computer system including a plurality of processing nodes, at least one resource provided for use by any of the processing nodes and a plurality of register sets. Each register set is provided in each of the processing nodes for storing in parallel use status information indicating whether the resource is in exclusive use status or not. The computer system can also include a plurality of request issue circuits, each being provided in each of the processing nodes, for issuing individually requests for exclusive use of the resource, a message exchanging circuit for serializing requests issued by the request issue circuits into a serialized order and broadcasting the request to all of the processing nodes in the serialized order and a plurality of status control circuits. Each status control circuit is provided in each of the processing nodes corresponding to each of the register sets to update individually a corresponding register set depending on use status information stored in the corresponding register set and each of the requests for exclusive use of the resource received at a corresponding node.
摘要翻译：一种包括多个处理节点的计算机系统，提供给任何处理节点使用的至少一个资源和多个寄存器组。在每个处理节点中提供每个寄存器组，用于并行地存储指示资源是否处于独占状态的状态信息。计算机系统还可以包括多个请求发布电路，每个请求发布电路分别设置在每个处理节点中，用于单独发出专用于资源的请求;消息交换电路，用于将请求发布电路发出的请求串行化为串行化以序列顺序向多个处理节点发送请求并将其发送给多个状态控制电路。每个状态控制电路被提供在与每个寄存器组相对应的每个处理节点中，以根据存储在相应寄存器组中的使用状态信息单独地更新对应的寄存器组，并且每个对专用的资源请求相应的节点。

5. 发明授权

US5617575A Interprocessor priority control system for multivector processor 失效
标题翻译：多处理器处理器优先级控制系统
公开(公告)号：US5617575A
公开(公告)日：1997-04-01
申请号：US170743
申请日：1993-12-21
申请人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F13/18 , G06F13/40 , G06F12/00 , G06F15/16
CPC分类号： G06F13/4027 , G06F13/18
摘要： In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
摘要翻译：在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。为存储控制单元中包含的优先级电路提供优先级位信息。在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为生成的优先级控制电路和所有优先级电路之间。

6. 发明授权

US5606686A Access control method for a shared main memory in a multiprocessor based upon a directory held at a storage location of data in the memory after reading data to a processor 失效
标题翻译：基于在将数据读取到处理器之后存储在存储器中的数据的存储位置的目录，在多处理器中的共享主存储器的访问控制方法
公开(公告)号：US5606686A
公开(公告)日：1997-02-25
申请号：US328759
申请日：1994-10-24
申请人： Toshiaki Tarui , Naonobu Sukegawa , Hiroaki Fujii , Katsuyoshi Kitai
发明人： Toshiaki Tarui , Naonobu Sukegawa , Hiroaki Fujii , Katsuyoshi Kitai
IPC分类号： G06F15/17 , G06F12/08 , G06F15/173
CPC分类号： G06F12/0817 , G06F12/0813 , G06F15/17393 , G06F2212/2542
摘要： A main memory shared by plural processing units in a parallel computer system is composed of plural partial main memories. A directory for each data line of the main memory is generated after the data line has been cached in one of the processing units. The directory is held in one of the partial main memories in place of the data line. The directory indicates a processing unit which has cached the data line. A status bit C provided for the data line is set. If a subsequent read request is given to the data line, the status C bit is checked and the directory is used to identify a processing unit that has cached the data line. The request is transferred to the identified processing unit, and the data line is transferred from that processing unit to the processing unit that has issued the request. If a processing unit that has cached the data line has replaced the data line, it is checked if there is a processing unit that has cached the data line. If there is none, the data line is written back into the one partial main memory. If there is, the data line is not written back. Another status bit RO is also used for each data line. It indicates if the data line is read only. If a data line is read only, generation of the directory and storing it in the partial main memory is prohibited.
摘要翻译：并行计算机系统中的多个处理单元共享的主存储器由多个部分主存储器构成。在数据线已被缓存在一个处理单元中之后，生成主存储器的每条数据线的目录。该目录被保存在一部分主存储器中以代替数据线。该目录指示已经缓存数据线的处理单元。设置为数据线提供的状态位C。如果向数据线提供后续的读取请求，则检查状态C位，并使用该目录来标识缓存数据线的处理单元。该请求被传送到所识别的处理单元，并且数据线从该处理单元传送到已经发出请求的处理单元。如果缓存数据线的处理单元已经取代了数据线，则检查是否存在缓存数据行的处理单元。如果没有，则数据线被写回到一个部分主存储器中。如果有，数据行不会被写回。每个数据线也使用另一个状态位RO。它指示数据行是否为只读。如果数据线是只读的，则禁止生成目录并将其存储在部分主存储器中。

7. 发明授权

US5590353A Vector processor adopting a memory skewing scheme for preventing degradation of access performance 失效
标题翻译：矢量处理器采用存储器偏移方案来防止访问性能下降
公开(公告)号：US5590353A
公开(公告)日：1996-12-31
申请号：US275388
申请日：1994-07-15
申请人： Tadayuki Sakakibara , Teruo Tanaka , Yoshiko Tamaki , Katsuyoshi Kitai , Yasuhiro Inagami
发明人： Tadayuki Sakakibara , Teruo Tanaka , Yoshiko Tamaki , Katsuyoshi Kitai , Yasuhiro Inagami
IPC分类号： G06F9/345 , G06F9/38 , G06F12/00 , G06F12/06 , G06F15/78 , G06F17/16 , G06F15/16
CPC分类号： G06F15/8061 , G06F9/345 , G06F9/3455 , G06F9/3824
摘要： A vector processor includes a storage control apparatus which incorporates an access request buffer unit equipped with an address decoding unit having address decoder circuits corresponding to all models of the vector processors belonging to a same machine series. By using model ID signals, the address decoding is selectively enabled by a selector. The address decoding unit equalizes the periodicities at which the address assignments to the memory modules are skewed or shifted for all the element parallelism factors of the processors belonging to the same machine series. Access request queue is provided in a necessary number of stages in precedence to an access request priority determining unit incorporated in the storage control apparatus.
摘要翻译：矢量处理器包括存储控制装置，该存储控制装置包括具有地址解码单元的访问请求缓冲单元，地址解码单元具有与属于同一机器系列的所有向量处理器模型对应的地址解码器电路。通过使用模型ID信号，地址解码由选择器选择性地启用。地址解码单元对属于同一机器系列的处理器的所有元素并行因子对存储器模块的地址分配进行偏移或偏移的周期性进行均衡。提供访问请求队列优先于包含在存储控制装置中的访问请求优先级确定单元的必要数量级。

8. 发明授权

US5339429A Parallel processing system and compiling method used therefor 失效
标题翻译：并行处理系统及其编译方法
公开(公告)号：US5339429A
公开(公告)日：1994-08-16
申请号：US880544
申请日：1992-05-08
申请人： Teruo Tanaka , Yasuhiro Inagami , Yoshiko Tamaki , Tadayuki Sakakibara , Katsuyoshi Kitai
发明人： Teruo Tanaka , Yasuhiro Inagami , Yoshiko Tamaki , Tadayuki Sakakibara , Katsuyoshi Kitai
IPC分类号： G06F9/45 , G06F12/02 , G06F15/167 , G06F9/44 , G06F12/12
CPC分类号： G06F8/44 , G06F12/0284 , G06F15/167
摘要： A parallel processing system includes tightly coupled multiprocessors. Each multiprocessor incorporates a local extended storage device which is a secondary storage device for a main storage device. The tightly coupled multiprocessors are connected with each other through a shared extended storage device. A compiler or preprocessor for the system analyzes the data to be allocated on the extended storage devices so that large scaled data accessed from each tightly-coupled multiprocessor are allocated on the local extended storage whereas the data to be accessed from a plurality of tightly-coupled multiprocessors are allocated on the shared extended storage.
摘要翻译：并行处理系统包括紧密耦合的多处理器。每个多处理器都包含一个本地扩展存储设备，它是主存储设备的辅助存储设备。紧密耦合的多处理器通过共享扩展存储设备彼此连接。用于系统的编译器或预处理器分析在扩展存储设备上要分配的数据，使得从每个紧密耦合的多处理器访问的大规模数据被分配在本地扩展存储器上，而从多个紧耦合多处理器分配在共享扩展存储上。

9. 发明授权

US5109499A Vector multiprocessor system which individually indicates the data element stored in common vector register 失效
标题翻译：矢量多处理器系统，分别指示存储在公共矢量寄存器中的数据元素
公开(公告)号：US5109499A
公开(公告)日：1992-04-28
申请号：US237418
申请日：1988-08-29
申请人： Yasuhiro Inagami , Yoshiko Tamaki , Katsuyoshi Kitai
发明人： Yasuhiro Inagami , Yoshiko Tamaki , Katsuyoshi Kitai
IPC分类号： G06F15/16 , G06F9/30 , G06F9/315 , G06F9/52 , G06F15/163 , G06F15/167 , G06F15/177 , G06F15/78 , G06F15/80 , G06F17/16
CPC分类号： G06F9/30032 , G06F15/8084 , G06F15/8092 , G06F9/30036 , G06F9/30109
摘要： At least one common vector register capable of being accessed from a plurality of vector processors constituting the multiprocessor is provided in order to transfer vector data among the vector processors at a high speed. The common vector register includes data fields each holding the value of vector data, access control sections provided corresponding to the respective data fields and showing the status of data access from the vector processor for synchronization of data sending and receiving, when the vector data is transferred among the different vector processors through the common vector register, and an access right section used for managing the number of the vector processor which is allowed to access the common vector register.
摘要翻译：提供能够从构成多处理器的多个向量处理器访问的至少一个公共向量寄存器，以便高速地在向量处理器之间传送向量数据。公共向量寄存器包括各自保存矢量数据值的数据字段，与各个数据字段对应地提供的访问控制部分，并且当矢量数据被传送时，显示来自矢量处理器的用于数据发送和接收同步的数据访问状态在通过公共向量寄存器的不同向量处理器中，以及用于管理允许访问公共向量寄存器的向量处理器的数量的访问权限部分。

10. 发明授权

US06826167B2 Mobile communication system 失效
标题翻译：移动通信系统
公开(公告)号：US06826167B2
公开(公告)日：2004-11-30
申请号：US09919913
申请日：2001-08-02
申请人： Tatsuaki Osafune , Katsuyoshi Kitai , Tohru Hoshi , Tomohiro Hotta , Koji Hirayama
发明人： Tatsuaki Osafune , Katsuyoshi Kitai , Tohru Hoshi , Tomohiro Hotta , Koji Hirayama
IPC分类号： H04Q728
CPC分类号： H04W76/14 , H04W92/02
摘要： A communication relay system is connected to a line switched mobile communication system adapted to accommodate therein mobile terminals through radio channels and a packet switched mobile communication system adapted to accommodate therein the mobile terminals through radio channels. When a connection request has been made to a portable terminal, the communication relay system judges whether the portable terminal of interest is connected either to the line switched mobile communication system or to the packet switched mobile communication system.
摘要翻译：通信中继系统连接到适于通过无线电信道容纳移动终端的线路交换移动通信系统和适于通过无线电信道在其中容纳移动终端的分组交换移动通信系统。当对便携式终端进行连接请求时，通信中继系统判断感兴趣的便携式终端是连接到线路交换移动通信系统还是与分组交换的移动通信系统连接。

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