专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08279670B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US08279670B2
公开(公告)日：2012-10-02
申请号：US12882507
申请日：2010-09-15
申请人： Takuya Futatsuyama , Yoshihisa Kondo , Noboru Shibata
发明人： Takuya Futatsuyama , Yoshihisa Kondo , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C8/00 , G11C11/5621 , G11C16/0483 , G11C2211/5641
摘要： A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller operative to control read, write and erase operations of the memory cell array. The memory cell array includes a first region having a first memory cell operative to retain N bits of data, and a second region having a second memory cell operative to retain M bits of data (where M is a natural number less than N). A data structure of address data received by the controller when accessing the first memory cell is the same as a data structure of address data received from the outside when accessing the second memory cell.
摘要翻译：根据实施例的非易失性半导体存储装置包括：包括电可重写存储器单元阵列的存储单元阵列，并且被配置为能够将N位数据（其中N是不小于2的自然数）存储在一个记忆体; 以及控制器，用于控制存储单元阵列的读，写和擦除操作。存储单元阵列包括具有第一存储器单元的第一区域，该第一存储器单元可操作以保留N位数据，以及具有第二存储单元的第二区域，该第二存储单元可操作以保持M位数据（其中M是小于N的自然数）。当访问第一存储器单元时，由控制器接收的地址数据的数据结构与在访问第二存储单元时从外部接收的地址数据的数据结构相同。

2. 发明申请

US20110069545A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20110069545A1
公开(公告)日：2011-03-24
申请号：US12882507
申请日：2010-09-15
申请人： Takuya FUTATSUYAMA , Yoshihisa Kondo , Noboru Shibata
发明人： Takuya FUTATSUYAMA , Yoshihisa Kondo , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C8/00 , G11C11/5621 , G11C16/0483 , G11C2211/5641
摘要： A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller operative to control read, write and erase operations of the memory cell array. The memory cell array includes a first region having a first memory cell operative to retain N bits of data, and a second region having a second memory cell operative to retain M bits of data (where M is a natural number less than N). A data structure of address data received by the controller when accessing the first memory cell is the same as a data structure of address data received from the outside when accessing the second memory cell.
摘要翻译：根据实施例的非易失性半导体存储装置包括：包括电可重写存储器单元阵列的存储单元阵列，并且被配置为能够将N位数据（其中N是不小于2的自然数）存储在一个记忆体; 以及控制器，用于控制存储单元阵列的读，写和擦除操作。存储单元阵列包括具有第一存储器单元的第一区域，该第一存储器单元可操作以保留N位数据，以及具有第二存储单元的第二区域，该第二存储单元可操作以保持M位数据（其中M是小于N的自然数）。当访问第一存储器单元时，由控制器接收的地址数据的数据结构与在访问第二存储单元时从外部接收的地址数据的数据结构相同。

3. 发明申请

US20050041515A1 Non-volatile semiconductor memory device, method for sub-block erase and electric device with the same 失效
标题翻译：非易失性半导体存储器件，子块擦除方法和电子器件相同
公开(公告)号：US20050041515A1
公开(公告)日：2005-02-24
申请号：US10678179
申请日：2003-10-06
申请人： Takuya Futatsuyama , Kenichi Imamiya , Koji Hosono , Noboru Shibata
发明人： Takuya Futatsuyama , Kenichi Imamiya , Koji Hosono , Noboru Shibata
IPC分类号： G11C16/02 , G11C16/04 , G11C16/16 , G11C16/34 , G11C8/02
CPC分类号： G11C16/3445 , G11C16/04 , G11C16/16 , G11C16/3436 , G11C16/3459 , G11C29/50004
摘要： After execution of sub-block erase (S2) for partly erasing a memory cell block, sub-block erase verify read is executed (S4). As a result of the sub-block erase verify read, if the sub-block erase is completed, then terminate the sub-block erase (S5). If otherwise the sub-block erase is not completed yet, then perform over-program verify read (S6) to thereby determine whether the cause of an event that a sub-block erase-verify result becomes “Fail” due to the deficiency of erase or the presence of an over-programmed cell or cells. If the result of such over-program verify read is “Pass,” then repeat execution of the sub-block erase verify read (S2). When the over-program verify read (S6) is “Fail,” output a Fail result and then complete the operation (S8).
摘要翻译：在执行用于部分擦除存储单元块的子块擦除（S2）之后，执行子块擦除验证读取（S4）。作为子块擦除验证读取的结果，如果子块擦除完成，则终止子块擦除（S5）。否则子块擦除尚未完成，则执行过程编程验证读取（S6），从而确定由于擦除不足导致子块擦除验证结果的事件的原因为“失败” 或存在过度编程的细胞或细胞。如果这种过程编程验证读取的结果是“通过”，则重复执行子块擦除验证读取（S2）。当过程程序验证读取（S6）为“失败”时，输出失败结果，然后完成操作（S8）。

4. 发明授权

US06903981B2 Non-volatile semiconductor memory device, method for sub-block erase and electric device with the same 失效
标题翻译：非易失性半导体存储器件，子块擦除方法和电子器件相同
公开(公告)号：US06903981B2
公开(公告)日：2005-06-07
申请号：US10678179
申请日：2003-10-06
申请人： Takuya Futatsuyama , Kenichi Imamiya , Koji Hosono , Noboru Shibata
发明人： Takuya Futatsuyama , Kenichi Imamiya , Koji Hosono , Noboru Shibata
IPC分类号： G11C16/02 , G11C16/04 , G11C16/16 , G11C16/34
CPC分类号： G11C16/3445 , G11C16/04 , G11C16/16 , G11C16/3436 , G11C16/3459 , G11C29/50004
摘要： After execution of sub-block erase (S2) for partly erasing a memory cell block, sub-block erase verify read is executed (S4). As a result of the sub-block erase verify read, if the sub-block erase is completed, then terminate the sub-block erase (S5). If otherwise the sub-block erase is not completed yet, then perform over-program verify read (S6) to thereby determine whether the cause of an event that a sub-block erase-verify result becomes “Fail” due to the deficiency of erase or the presence of an over-programmed cell or cells. If the result of such over-program verify read is “Pass,” then repeat execution of the sub-block erase verify read (S2). When the over-program verify read (S6) is “Fail,” output a Fail result and then complete the operation (S8).
摘要翻译：在执行用于部分擦除存储单元块的子块擦除（S 2）之后，执行子块擦除验证读取（S 4）。作为子块擦除验证读取的结果，如果子块擦除完成，则终止子块擦除（S 5）。否则子块擦除尚未完成，则执行过程编程验证读取（S 6），从而确定子块擦除验证结果由于不足而导致的“失败”事件的原因擦除或过度编程的细胞或细胞的存在。如果这种过程编程验证读取的结果为“通过”，则重复执行子块擦除验证读取（S 2）。当过程程序验证读取（S 6）为“失败”时，输出失败结果，然后完成操作（S 8）。

5. 发明授权

US07173862B2 Non-volatile semiconductor memory device, method for sub-block erase and electric device with the same 失效
标题翻译：非易失性半导体存储器件，子块擦除方法和电子器件相同
公开(公告)号：US07173862B2
公开(公告)日：2007-02-06
申请号：US11138427
申请日：2005-05-27
申请人： Takuya Futatsuyama , Kenichi Imamiya , Koji Hosono , Noboru Shibata
发明人： Takuya Futatsuyama , Kenichi Imamiya , Koji Hosono , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3445 , G11C16/04 , G11C16/16 , G11C16/3436 , G11C16/3459 , G11C29/50004
摘要： After execution of sub-block erase (S2) for partly erasing a memory cell block, sub-block erase verify read is executed (S4). As a result of the sub-block erase verify read, if the sub-block erase is completed, then terminate the sub-block erase (S5). If otherwise the sub-block erase is not completed yet, then perform over-program verify read (S6) to thereby determine whether the cause of an event that a sub-block erase-verify result becomes “Fail” due to the deficiency of erase or the presence of an over-programmed cell or cells. If the result of such over-program verify read is “Pass,” then repeat execution of the sub-block erase verify read (S2). When the over-program verify read (S6) is “Fail,” output a Fail result and then complete the operation (S8).
摘要翻译：在执行用于部分擦除存储单元块的子块擦除（S 2）之后，执行子块擦除验证读取（S 4）。作为子块擦除验证读取的结果，如果子块擦除完成，则终止子块擦除（S 5）。否则子块擦除尚未完成，则执行过程编程验证读取（S 6），从而确定子块擦除验证结果由于不足而导致的“失败”事件的原因擦除或过度编程的细胞或细胞的存在。如果这种过程编程验证读取的结果为“通过”，则重复执行子块擦除验证读取（S 2）。当过程程序验证读取（S 6）为“失败”时，输出失败结果，然后完成操作（S 8）。

6. 发明申请

US20050219909A1 Non-volatile semiconductor memory device, method for sub-block erase and electric device with the same 失效
公开(公告)号：US20050219909A1
公开(公告)日：2005-10-06
申请号：US11138427
申请日：2005-05-27
申请人： Takuya Futatsuyama , Kenichi Imamiya , Koji Hosono , Noboru Shibata
发明人： Takuya Futatsuyama , Kenichi Imamiya , Koji Hosono , Noboru Shibata
IPC分类号： G11C16/02 , G11C16/04 , G11C16/16 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3445 , G11C16/04 , G11C16/16 , G11C16/3436 , G11C16/3459 , G11C29/50004
摘要： After execution of sub-block erase (S2) for partly erasing a memory cell block, sub-block erase verify read is executed (S4). As a result of the sub-block erase verify read, if the sub-block erase is completed, then terminate the sub-block erase (S5). If otherwise the sub-block erase is not completed yet, then perform over-program verify read (S6) to thereby determine whether the cause of an event that a sub-block erase-verify result becomes “Fail” due to the deficiency of erase or the presence of an over-programmed cell or cells. If the result of such over-program verify read is “Pass,” then repeat execution of the sub-block erase verify read (S2). When the over-program verify read (S6) is “Fail,” output a Fail result and then complete the operation (S8).

7. 发明授权

US08855297B2 Device and authentication method therefor 有权
标题翻译：设备及认证方法
公开(公告)号：US08855297B2
公开(公告)日：2014-10-07
申请号：US13524475
申请日：2012-06-15
申请人： Yuji Nagai , Taku Kato , Tatsuyuki Matsushita , Toshihiro Suzuki , Noboru Shibata
发明人： Yuji Nagai , Taku Kato , Tatsuyuki Matsushita , Toshihiro Suzuki , Noboru Shibata
IPC分类号： G06F21/24
CPC分类号： H04L9/0816 , G11B20/00362 , G11B20/00427 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information.
摘要翻译：根据一个实施例，一种认证方法包括：通过在单向功能操作中用存储器会话密钥计算秘密识别信息，通过存储器生成第一认证信息，发送加密的秘密识别信息，家庭密钥块和第一认证信息发送到主机，并且由主机通过计算通过用单向功能操作中的主机会话密钥对加密的秘密识别信息进行解密而生成的秘密识别信息来生成第二认证信息。该方法还包括由主机将第一认证信息与第二认证信息进行比较。

8. 发明授权

US08812843B2 Device and authentication method therefor 有权
标题翻译：设备及认证方法
公开(公告)号：US08812843B2
公开(公告)日：2014-08-19
申请号：US13524843
申请日：2012-06-15
申请人： Yuji Nagai , Taku Kato , Tatsuyuki Matsushita , Toshihiro Suzuki , Noboru Shibata
发明人： Yuji Nagai , Taku Kato , Tatsuyuki Matsushita , Toshihiro Suzuki , Noboru Shibata
IPC分类号： H04L9/32
CPC分类号： H04L9/0816 , G11B20/00362 , G11B20/00427 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, a device includes first and second data generator, a one-way function processor, and a data output interface. The first data generator generates a second key by encrypting a host constant with a first key in AES operation. The second data generator generates a session key by encrypting a random number with a second key in AES operation. The one-way function processor generates authentication information by processing secret identification information with the session key in one-way function operation. The data output interface outputs the encrypted secret identification information, a family key block, and the authentication information to outside of the device.
摘要翻译：根据一个实施例，设备包括第一和第二数据生成器，单向功能处理器和数据输出接口。第一个数据生成器通过AES操作中的第一个密钥加密主机常数来生成第二个密钥。第二数据生成器通过在AES操作中用第二密钥加密随机数生成会话密钥。单向功能处理器通过在单向功能操作中通过会话密钥处理秘密识别信息来生成认证信息。数据输出接口将加密的秘密识别信息，家庭密钥块和认证信息输出到设备外部。

9. 发明授权

US08732466B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08732466B2
公开(公告)日：2014-05-20
申请号：US13524894
申请日：2012-06-15
申请人： Yuji Nagai , Toshihiro Suzuki , Noboru Shibata , Taku Kato , Tatsuyuki Matsushita
发明人： Yuji Nagai , Toshihiro Suzuki , Noboru Shibata , Taku Kato , Tatsuyuki Matsushita
IPC分类号： H04L9/32
CPC分类号： H04L9/0816 , G11B20/00086 , G11B20/00115 , G11B20/0021 , G11B2220/2516 , G11B2220/60 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, a device includes a first memory area to store a first key. A second memory area stores encrypted secret identification (ID) information generated from secret ID information with a family key. A third memory area stores a family key block including data generated from the family key with an ID key. An authentication module performs authentication. A second key is generated from a first number with the first key, a session key is generated from a random number with the second key, and authentication information is generated from the secret ID information with the session key. The encrypted secret ID information, family key block and the authentication information is output.
摘要翻译：根据一个实施例，设备包括用于存储第一密钥的第一存储区域。第二存储区域存储从秘密ID信息生成的加密的秘密标识（ID）信息与家庭密钥。第三存储区域存储包括具有ID密钥的家族密钥产生的数据的家庭密钥块。认证模块执行认证。从具有第一密钥的第一号码生成第二密钥，从具有第二密钥的随机数生成会话密钥，并且从具有会话密钥的秘密ID信息生成认证信息。输出加密的秘密ID信息，家庭密钥块和认证信息。

10. 发明授权

US08687420B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08687420B2
公开(公告)日：2014-04-01
申请号：US13589842
申请日：2012-08-20
申请人： Noboru Shibata , Kazunori Kanebako
发明人： Noboru Shibata , Kazunori Kanebako
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C29/00 , G11C2211/5642 , G11C2211/5648
摘要： A semiconductor memory device which includes multi-bit memory cells that store multi-bit data and memory cells that store data of fewer bits then that of the multi-bit data. Thus, the semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h≦n) data is stored in a memory MLC of a first region MLB, and i-bit (i
摘要翻译：一种半导体存储器件，包括存储多位数据的多位存储器单元和存储少位数据以及多位数据的数据的存储器单元。因此，半导体存储器件包括用于存储一个单元的n位（其中n是等于或大于2的自然数）的多个存储器单元。在多个存储单元中，h位（h＆nlE; n）数据被存储在第一区域MLB的存储器MLC中，i位（i

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式