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1. 发明授权

US4352726A Ion selective field-effect sensor 失效
标题翻译：离子选择性场效应传感器
公开(公告)号：US4352726A
公开(公告)日：1982-10-05
申请号：US201637
申请日：1980-10-28
申请人： Takuo Sugano , Eiji Niki , Yoichi Okabe , Tatsuo Akiyama
发明人： Takuo Sugano , Eiji Niki , Yoichi Okabe , Tatsuo Akiyama
IPC分类号： G01N27/00 , G01N27/414 , H01L29/78 , G01N27/30
CPC分类号： G01N27/414
摘要： An ion selective field-effect sensor selectively sensitive to a particular cation to be measured is disclosed. In the sensor is used a giant heterocyclic compound selectively forming a complex with the particular cation as an ion sensitive film provided on a surface of a field-effect semiconductor device.
摘要翻译：公开了对要测量的特定阳离子选择性敏感的离子选择性场效应传感器。在传感器中使用巨型杂环化合物，其选择性地与特定阳离子形成复合物作为设置在场效应半导体器件的表面上的离子敏感膜。

2. 发明授权

US5643046A Polishing method and apparatus for detecting a polishing end point of a semiconductor wafer 失效
标题翻译：用于检测半导体晶片的抛光终点的抛光方法和装置
公开(公告)号：US5643046A
公开(公告)日：1997-07-01
申请号：US390529
申请日：1995-02-17
申请人： Ichiro Katakabe , Naoto Miyashita , Tatsuo Akiyama
发明人： Ichiro Katakabe , Naoto Miyashita , Tatsuo Akiyama
IPC分类号： B24B37/013 , B24B49/04 , H01L21/304 , B24B7/22 , B24B49/12
CPC分类号： B24B37/013 , B24B49/04
摘要： A polishing method and apparatus are provided for detecting the polishing end point of a semi-conductor wafer having a polishing film and a stopper film formed thereon. First driving means are provided having a first drive shaft for rotating a polishing plate and a polishing cloth thereon. Second driving means having a second rotatable drive shaft are also provided. Mounting means for mounting the semi-conductor wafer is adapted to be rotated by the second driving means for polishing the wafer. Energy supplying means for supplying prescribed energy to the semi-conductor wafer are also included. Finally, detecting means for detecting a polishing end point of the polishing film is included and detects a variation of the energy supplied to the semi-conductor wafer. Different types of energy can be utilized such as infrared light and a vibration wave.
摘要翻译：提供了一种抛光方法和装置，用于检测在其上形成有抛光膜和阻挡膜的半导体晶片的研磨终点。第一驱动装置设置有用于使研磨板和抛光布旋转的第一驱动轴。还提供具有第二可旋转驱动轴的第二驱动装置。用于安装半导体晶片的安装装置适于通过用于抛光晶片的第二驱动装置旋转。还包括用于向半导体晶片提供规定能量的能量供给装置。最后，包括用于检测抛光膜的抛光终点的检测装置，并且检测提供给半导体晶片的能量的变化。可以使用不同类型的能量，例如红外光和振动波。

3. 发明授权

US5374835A Field effect transistor using compound semiconductor 失效
标题翻译：使用化合物半导体的场效应晶体管
公开(公告)号：US5374835A
公开(公告)日：1994-12-20
申请号：US63654
申请日：1993-05-20
申请人： Kizashi Shimada , Mayumi Kamura , Tatsuo Akiyama
发明人： Kizashi Shimada , Mayumi Kamura , Tatsuo Akiyama
IPC分类号： H01L29/812 , H01L21/338 , H01L29/423 , H01L29/778 , H01L29/80 , H01L31/112
CPC分类号： H01L29/42316
摘要： A compound semiconductor device such as HEMTs (High Electron Mobility Transistors), metal semiconductor field effect transistors, and the like includes a compound semiconductor substrate having an active region, an insulating film provided over the semiconductor substrate, source and drain electrodes provided on the active region, and a gate electrode located between the source and drain electrodes. In the structure, the gate electrode has a lower electrode portion for providing a Schottky barrier contact with the active region through an opening of the insulating film, and an upper electrode portion provided on the insulating film to extend toward only the drain electrode.
摘要翻译：诸如HEMT（高电子迁移率晶体管），金属半导体场效应晶体管等的化合物半导体器件包括具有有源区的化合物半导体衬底，设置在半导体衬底上的绝缘膜，设置在有源区上的源极和漏极以及位于源极和漏极之间的栅电极。在该结构中，栅电极具有用于通过绝缘膜的开口与有源区提供肖特基势垒接触的下电极部分和设置在绝缘膜上以仅向漏电极延伸的上电极部分。

4. 发明授权

US4700455A Method of fabricating Schottky gate-type GaAs field effect transistor 失效
标题翻译：制造肖特基栅型GaAs场效应晶体管的方法
公开(公告)号：US4700455A
公开(公告)日：1987-10-20
申请号：US792825
申请日：1985-10-30
申请人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
发明人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
IPC分类号： H01L21/338 , H01L29/812 , H01L21/265
CPC分类号： H01L29/66878 , H01L29/812
摘要： A method of manufacturing a semiconductor device wherein an insulating film of silicon dioxide is provided on the sidewalls of a gate electrode. This silicon dioxide film is used to define the length of the gate region during formation of the source and drain regions by ion implantation, and to accurately position the gate electrode relative to the source and drain regions.
摘要翻译：一种制造半导体器件的方法，其中二极管的绝缘膜设置在栅电极的侧壁上。该二氧化硅膜用于通过离子注入来形成源极和漏极区域期间限定栅极区域的长度，并且相对于源极和漏极区域精确地定位栅电极。

5. 发明申请

US20140044377A1 SHOT IMAGE PROCESSING SYSTEM, SHOT IMAGE PROCESSING METHOD, MOBILE TERMINAL, AND INFORMATION PROCESSING APPARATUS 审中-公开
标题翻译：拍摄图像处理系统，拍摄图像处理方法，移动终端和信息处理设备
公开(公告)号：US20140044377A1
公开(公告)日：2014-02-13
申请号：US14112525
申请日：2012-03-07
申请人： Shoji Yachida , Daisuke Nishiwaki , Tatsuo Akiyama
发明人： Shoji Yachida , Daisuke Nishiwaki , Tatsuo Akiyama
IPC分类号： G06T7/00
CPC分类号： G06T7/00 , H04N1/00244 , H04N1/00408 , H04N1/00973 , H04N5/232 , H04N2201/0039 , H04N2201/0096
摘要： A shot image processing system (100) includes a mobile terminal (1) that shoots an image of a conversion target region containing a character and/or an image, and displays the shot image containing the conversion target region on a display unit; a server that receives the shot image from the mobile terminal (1), wherein the server (2) determines a specifying method for specifying a location of the conversion target region in the received shot image, and transmits the determined specifying method to the mobile terminal, and the mobile terminal (1) specifies the location of the conversion target region in the shot image based on the specifying method received from the server (2), converts the conversion target region specified in the shot image into a prescribed format, and displays a converted image obtained by the conversion on the display unit (16).
摘要翻译：拍摄图像处理系统（100）包括：拍摄包含字符和/或图像的转换目标区域的图像的移动终端（1），并将包含转换对象区域的拍摄图像显示在显示单元上; 从移动终端（1）接收拍摄图像的服务器，其中服务器（2）确定用于指定接收到的镜头图像中的转换目标区域的位置的指定方法，并将所确定的指定方法发送到移动终端，并且移动终端（1）基于从服务器（2）接收的指定方法来指定拍摄图像中的转换目标区域的位置，将拍摄图像中指定的转换目标区域转换为规定格式，并且显示通过在显示单元（16）上的转换获得的转换图像。

6. 发明授权

US5229323A Method for manufacturing a semiconductor device with Schottky electrodes 失效
标题翻译：制造具有肖特基电极的半导体器件的方法
公开(公告)号：US5229323A
公开(公告)日：1993-07-20
申请号：US846985
申请日：1992-03-09
申请人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
发明人： Kizashi Shimada , Tatsuo Akiyama , Yutaka Koshino
IPC分类号： H01L21/263 , H01L21/285 , H01L21/338
CPC分类号： H01L29/66863 , H01L21/2633 , H01L21/28581 , Y10S148/139 , Y10S148/14
摘要： A method for manufacturing a semiconductor device with a Schottky electrode includes the steps of subjecting the surface of a GaAs substrate to a sputtering etching process in a sputtering processing chamber of a sputtering device; and depositing Schottky electrode material by sputtering on the surface of the substrate to form a Schottky electrode in the processing chamber without exposing the substrate to the atmosphere.
摘要翻译：制造具有肖特基电极的半导体器件的方法包括以下步骤：在溅射装置的溅射处理室中对GaAs衬底的表面进行溅射蚀刻工艺; 并通过溅射将肖特基电极材料沉积在衬底的表面上以在处理室中形成肖特基电极，而不将衬底暴露于大气中。

7. 发明授权

US09430711B2 Feature point matching device, feature point matching method, and non-transitory computer readable medium storing feature matching program 有权
标题翻译：特征点匹配装置，特征点匹配方法和非暂态计算机可读介质存储特征匹配程序
公开(公告)号：US09430711B2
公开(公告)日：2016-08-30
申请号：US13984004
申请日：2011-11-01
申请人： Tatsuo Akiyama
发明人： Tatsuo Akiyama
IPC分类号： G06K9/46 , G06K9/62 , G06T7/00
CPC分类号： G06K9/46 , G06K9/6211 , G06K2209/01 , G06T7/74
摘要： A feature point matching device includes a position feature generation unit for generating a position feature quantity for a feature point based on a position of the feature point included in an image, a pixel value feature generation unit for generating a pixel value feature quantity for the feature point based on a pixel value of the feature point included in the image, and a feature matching unit for matching a first feature point and a second feature point based on a degree of matching between a first position feature quantity generated from a first image and a second position feature quantity generated from a second image and a degree of matching between a first pixel value feature quantity generated from the first image and a second pixel value feature quantity generated from the second image.
摘要翻译：特征点匹配装置包括：位置特征生成单元，用于基于图像中包含的特征点的位置生成特征点的位置特征量;像素值特征生成单元，生成特征的像素值特征量基于图像中包含的特征点的像素值的特征点，以及基于从第一图像生成的第一位置特征量与第二特征点之间的匹配度来匹配第一特征点和第二特征点的特征匹配单元从第二图像生成的第二位置特征量和从第一图像生成的第一像素值特征量与从第二图像生成的第二像素值特征量之间的匹配度。

8. 发明申请

US20100239172A1 FEATURE POINT ARRANGEMENT CHECKING DEVICE, IMAGE CHECKING DEVICE, METHOD THEREFOR, AND PROGRAM 有权
标题翻译：特征点安装检查设备，图像检查设备，其方法和程序
公开(公告)号：US20100239172A1
公开(公告)日：2010-09-23
申请号：US12734559
申请日：2008-11-10
申请人： Tatsuo Akiyama
发明人： Tatsuo Akiyama
IPC分类号： G06K9/46
CPC分类号： G06T7/33
摘要： The arrangements of feature points are computed based on feature points acquired from checking target images. The feature amount having invariants as elements regarding a geometrical transformation is generated for each of the checking target images based on a computed result. And when checking whether or not the feature point arrangements of the checking target images are the same feature point arrangements by using the feature point amounts of the checking target images, at least each of the feature point arrangements that are bases for generating the feature amounts is stored, and a parameter regarding the geometrical transformation is computed based on the feature point arrangements of the checking target images. By utilizing the computed parameter regarding the geometrical transformation, whether or not the feature point arrangements of the checking target images are the same feature point arrangements is checked.
摘要翻译：特征点的布置基于从检查目标图像获得的特征点来计算。基于计算结果，针对每个检查对象图像生成具有关于几何变换的元素的不变量的特征量。并且当通过使用检查对象图像的特征点量来检查检查对象图像的特征点排列是否是相同的特征点排列时，作为生成特征量的基础的至少每个特征点排列是存储，并且基于检查对象图像的特征点排列来计算关于几何变换的参数。通过利用关于几何变换的计算参数，检查检查对象图像的特征点排列是否相同的特征点布置。

9. 发明授权

US06775816B2 Semiconductor design/fabrication system, semiconductor design/fabrication method and semiconductor design/fabrication program 有权
标题翻译：半导体设计/制造系统，半导体设计/制造方法和半导体设计/制造程序
公开(公告)号：US06775816B2
公开(公告)日：2004-08-10
申请号：US10327114
申请日：2002-12-24
申请人： Yoshiyuki Sato , Shigeki Sugimoto , Tatsuo Akiyama
发明人： Yoshiyuki Sato , Shigeki Sugimoto , Tatsuo Akiyama
IPC分类号： G06F1750
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor design/fabrication system which combines a plurality of function blocks and arranges the combined function blocks on a chip, comprising: a function block selector which selects the function blocks to be arranged on the same chip from a plurality of function blocks for each of which a critical area indicating a range where defective products occur due to existence of defects is known; a chip information calculator which calculates a sum of the critical areas on each of the selected function blocks; an yield calculator which calculates an yield based on a calculation result of the chip information calculator and defect occurrence rate information of a chip fabrication line; a cost delivery time information calculator which calculates information relating to fabrication cost and delivery time of the chip based on a calculation result of the yield calculator and fabrication management information relating to cost and fabrication period of the chip fabrication line; and a combination selector which selects a combination of the function blocks constituting the chip based on the information relating to the fabrication cost and the delivery time of the chip calculated by the cost delivery time information calculator.
摘要翻译：一种组合多个功能块并将组合功能块布置在芯片上的半导体设计/制造系统，包括：功能块选择器，从多个功能块中选择要布置在同一芯片上的功能块，这是一个关键区域，表明由于存在缺陷而出现缺陷产品的范围; 芯片信息计算器，其计算每个所选择的功能块上的关键区域的总和; 收益率计算器，其基于芯片信息计算器的计算结果和芯片制造线的缺陷发生率信息来计算收益; 成本交付时间信息计算器，其基于收益计算器的计算结果和与芯片制造线的成本和制造周期相关的制造管理信息来计算与芯片的制造成本和交付时间有关的信息; 以及组合选择器，其基于与由成本递送时间信息计算器计算的芯片的制造成本和输送时间有关的信息来选择构成芯片的功能块的组合。

10. 发明授权

US5031021A Semiconductor device with a high breakdown voltage 失效
标题翻译：具有高击穿电压的半导体器件
公开(公告)号：US5031021A
公开(公告)日：1991-07-09
申请号：US905958
申请日：1986-09-11
申请人： Yoshiro Baba , Kazuo Tsuru , Tatsuo Akiyama , Yutaka Koshino
发明人： Yoshiro Baba , Kazuo Tsuru , Tatsuo Akiyama , Yutaka Koshino
IPC分类号： H01L29/73 , H01L21/331 , H01L29/04 , H01L29/06 , H01L29/40 , H01L29/732
CPC分类号： H01L29/405 , H01L29/04 , H01L29/0619 , H01L29/408
摘要： There is disclosed a power transistor comprising a semiconductor substrate having a PN junction exposed on a major surface of the semiconductor substrate, and a semiinsulative polysilicon film formed on the major surface, the polysilicon film covering the PN junction, the polysilicon film containing at least one of carbon, oxygen, and nitrogen, and the polysilicon film having a thickness of about 3000 .ANG..
摘要翻译：公开了一种功率晶体管，其包括具有在该半导体衬底的主表面上露出的PN结的半导体衬底和形成在该主表面上的半绝缘性多晶硅膜，该多晶硅膜覆盖该PN结，该多晶硅膜含有至少一个的碳，氧和氮，以及多晶硅膜的厚度约为3000纳米。

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