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1. 发明申请

US20100061142A1 MEMORY ELEMENT AND MEMORY APPARATUS 审中-公开
标题翻译：记忆元素和记忆装置
公开(公告)号：US20100061142A1
公开(公告)日：2010-03-11
申请号：US12532552
申请日：2007-11-30
申请人： Koji Arita , Takeshi Takagi , Takumi Mikawa , Yoshio Kawashima , Zhiqiang Wei
发明人： Koji Arita , Takeshi Takagi , Takumi Mikawa , Yoshio Kawashima , Zhiqiang Wei
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/76 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147
摘要： Memory elements (3) arranged in matrix in a memory apparatus (21), each includes a resistance variable element (1) which changes an electrical resistance value in response to an applied electrical pulse having a positive polarity or a negative polarity and maintains the changed electrical resistance value, and a current suppressing element (2) for suppressing a current flowing when the electrical pulse is applied to the resistance variable element. The current suppressing element includes a first electrode, a second electrode, and a current suppressing layer provided between the first electrode and the second electrode, and the current suppressing layer comprises SiNx (x: positive actual number).
摘要翻译：在存储装置（21）中排列成矩阵的存储元件（3），每个包括电阻变化元件（1），其响应于所施加的具有正极性或负极性的电脉冲改变电阻值，并保持改变电阻值和电流抑制元件（2），用于抑制当电脉冲施加到电阻可变元件时流动的电流。电流抑制元件包括第一电极，第二电极和设置在第一电极和第二电极之间的电流抑制层，并且电流抑制层包括SiNx（x：正实数）。

2. 发明申请

US20100090193A1 NONVOLATILE MEMORY ELEMENT ARRAY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储元件阵列及其制造方法
公开(公告)号：US20100090193A1
公开(公告)日：2010-04-15
申请号：US12445380
申请日：2007-10-12
申请人： Takumi Mikawa , Takeshi Takagi , Yoshio Kawashima , Koji Arita
发明人： Takumi Mikawa , Takeshi Takagi , Yoshio Kawashima , Koji Arita
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/124 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1683
摘要： A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).
摘要翻译：下电极（22）设置在半导体芯片基板（26）上。下部电极（22）从上方被第一层间绝缘层（27）覆盖。第一接触孔（28）设置在下电极（22）上以穿透第一层间绝缘层（27）。嵌入形成电阻变化层（24）的低电阻层（29）以填充第一接触孔（28）。在第一层间绝缘层（27）和低电阻层（29）上设置有高电阻层（30）。电阻变化层（24）由包含单层高电阻层（30）和单层低电阻层（29）的多层电阻层形成。形成存储器部分（25）的低电阻层（29）至少与其相邻的存储器部分（25）隔离。

3. 发明授权

US07981760B2 Method for manufacturing nonvolatile storage element and method for manufacturing nonvolatile storage device 有权
标题翻译：非易失性存储元件的制造方法及其制造方法
公开(公告)号：US07981760B2
公开(公告)日：2011-07-19
申请号：US12669812
申请日：2009-05-07
申请人： Yoshio Kawashima , Takumi Mikawa , Takeshi Takagi , Koji Arita
发明人： Yoshio Kawashima , Takumi Mikawa , Takeshi Takagi , Koji Arita
IPC分类号： H01L21/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.
摘要翻译：一种用于制造使上部电极和下部电极之间的形状偏移最小化的非易失性存储元件的方法，包括：依次沉积导电的连接电极层，下部电极层和可变电阻层的非贵金属氮化物，并且是导电的，由贵金属制成的上电极层和掩模层; 将掩模层形成为预定形状; 通过使用掩模层作为掩模通过蚀刻将上电极层，可变电阻层和下电极层形成为预定形状; 并且同时去除已经通过蚀刻暴露的掩模和连接电极层的区域。

4. 发明授权

US07960770B2 Nonvolatile memory element array with storing layer formed by resistance variable layers 有权
标题翻译：具有由电阻变化层形成的存储层的非易失存储元件阵列
公开(公告)号：US07960770B2
公开(公告)日：2011-06-14
申请号：US12445380
申请日：2007-10-12
申请人： Takumi Mikawa , Takeshi Takagi , Yoshio Kawashima , Koji Arita
发明人： Takumi Mikawa , Takeshi Takagi , Yoshio Kawashima , Koji Arita
IPC分类号： H01L29/76
CPC分类号： H01L27/101 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/124 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1683
摘要： A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).
摘要翻译：下电极（22）设置在半导体芯片基板（26）上。下部电极（22）从上方被第一层间绝缘层（27）覆盖。第一接触孔（28）设置在下电极（22）上以穿透第一层间绝缘层（27）。嵌入形成电阻变化层（24）的低电阻层（29），以填充第一接触孔（28）。在第一层间绝缘层（27）和低电阻层（29）上设置有高电阻层（30）。电阻变化层（24）由包含单层高电阻层（30）和单层低电阻层（29）的多层电阻层形成。形成存储器部分（25）的低电阻层（29）至少与其相邻的存储器部分（25）隔离。

5. 发明申请

US20100190313A1 METHOD FOR MANUFACTURING NONVOLATILE STORAGE ELEMENT AND METHOD FOR MANUFACTURING NONVOLATILE STORAGE DEVICE 有权
标题翻译：制造非易失性存储元件的方法和制造非易失存储器件的方法
公开(公告)号：US20100190313A1
公开(公告)日：2010-07-29
申请号：US12669812
申请日：2009-05-07
申请人： Yoshio Kawashima , Takumi Mikawa , Takeshi Takagi , Koji Arita
发明人： Yoshio Kawashima , Takumi Mikawa , Takeshi Takagi , Koji Arita
IPC分类号： H01L21/8246
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer, into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.
摘要翻译：一种用于制造使上部电极和下部电极之间的形状偏移最小化的非易失性存储元件的方法，包括：依次沉积导电的连接电极层，下部电极层和可变电阻层的非贵金属氮化物，并且是导电的，由贵金属制成的上电极层和掩模层; 形成掩模层，形成预定的形状; 通过使用掩模层作为掩模通过蚀刻将上电极层，可变电阻层和下电极层形成为预定形状; 并且同时去除已经通过蚀刻暴露的掩模和连接电极层的区域。

6. 发明授权

US08394669B2 Resistance variable element and resistance variable memory device 有权
标题翻译：电阻可变元件和电阻变量存储器件
公开(公告)号：US08394669B2
公开(公告)日：2013-03-12
申请号：US13128575
申请日：2010-07-12
申请人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
IPC分类号： H01L21/02 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1666 , H01L45/1675
摘要： A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.
摘要翻译：在根据本发明的通孔交叉点结构存储装置中使用的电阻可变元件（100）和包括电阻可变元件的电阻变化存储装置包括基板（7）和层间绝缘层（ 3），并且具有形成贯通层间绝缘层的通孔（4）的构造，在通孔的外侧形成有包含过渡金属氧化物的第一电阻变化层（2），在通孔内形成有包含过渡金属氧化物的第二电阻变化层（5），第一电阻变化层的电阻率与第二电阻变化层不同，第一电阻变化层和第二电阻变化层接触彼此仅在更靠近基板的通孔的开口（20）中。

7. 发明申请

US20110114912A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110114912A1
公开(公告)日：2011-05-19
申请号：US12867437
申请日：2009-02-09
申请人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
发明人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/101 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A nonvolatile semiconductor memory device (100) comprises a substrate (102) provided with a transistor (101); a first interlayer insulating layer (103) formed over the substrate to cover the transistor; a first contact plug (104) formed in the first interlayer insulating layer and electrically connected to either of a drain electrode (101a) or a source electrode (101b) of the transistor, and a second contact plug (105) formed in the first interlayer insulating layer and electrically connected to the other of the drain electrode or the source electrode of the transistor; a resistance variable layer (106) formed to cover a portion of the first contact plug; a first wire (107) formed on the resistance variable layer; and a second wire (108) formed to cover a portion of the second contact plug; an end surface of the resistance variable layer being coplanar with an end surface of the first wire.
摘要翻译：非易失性半导体存储器件（100）包括设置有晶体管（101）的衬底（102）; 形成在所述衬底上以覆盖所述晶体管的第一层间绝缘层（103）形成在所述第一层间绝缘层中并电连接到所述晶体管的漏电极（101a）或源电极（101b）中的任一个的第一接触插塞（104）和形成在所述第一中间层绝缘层并与晶体管的漏电极或源电极中的另一个电连接; 形成为覆盖所述第一接触插塞的一部分的电阻变化层（106）形成在电阻变化层上的第一线（107）以及形成为覆盖所述第二接触插塞的一部分的第二线（108）所述电阻变化层的端面与所述第一线的端面共面。

8. 发明授权

US08537605B2 Nonvolatile semiconductor memory device having coplanar surfaces at resistance variable layer and wiring layer and manufacturing method thereof 有权
标题翻译：在电阻变化层和布线层具有共面的非易失性半导体存储器件及其制造方法
公开(公告)号：US08537605B2
公开(公告)日：2013-09-17
申请号：US12867437
申请日：2009-02-09
申请人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
发明人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
IPC分类号： G11C11/14
CPC分类号： H01L27/101 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A nonvolatile semiconductor memory device (100) comprises a substrate (102) provided with a transistor (101); a first interlayer insulating layer (103) formed over the substrate to cover the transistor; a first contact plug (104) formed in the first interlayer insulating layer and electrically connected to either of a drain electrode (101a) or a source electrode (101b) of the transistor, and a second contact plug (105) formed in the first interlayer insulating layer and electrically connected to the other of the drain electrode or the source electrode of the transistor; a resistance variable layer (106) formed to cover a portion of the first contact plug; a first wire (107) formed on the resistance variable layer; and a second wire (108) formed to cover a portion of the second contact plug; an end surface of the resistance variable layer being coplanar with an end surface of the first wire.
摘要翻译：非易失性半导体存储器件（100）包括设置有晶体管（101）的衬底（102）; 形成在所述衬底上以覆盖所述晶体管的第一层间绝缘层（103）形成在所述第一层间绝缘层中并电连接到所述晶体管的漏电极（101a）或源电极（101b）中的任一个的第一接触插塞（104）和形成在所述第一中间层绝缘层并与晶体管的漏电极或源电极中的另一个电连接; 形成为覆盖所述第一接触插塞的一部分的电阻变化层（106）形成在电阻变化层上的第一线（107）以及形成为覆盖所述第二接触插塞的一部分的第二线（108）所述电阻变化层的端面与所述第一线的端面共面。

9. 发明申请

US20110220862A1 RESISTANCE VARIABLE ELEMENT AND RESISTANCE VARIABLE MEMORY DEVICE 有权
标题翻译：电阻可变元件和电阻可变存储器件
公开(公告)号：US20110220862A1
公开(公告)日：2011-09-15
申请号：US13128575
申请日：2010-07-12
申请人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1666 , H01L45/1675
摘要： A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.
摘要翻译：在根据本发明的通孔交叉点结构存储装置中使用的电阻可变元件（100）和包括电阻可变元件的电阻变化存储装置包括基板（7）和层间绝缘层（ 3），并且具有形成贯通层间绝缘层的通孔（4）的构造，在通孔的外侧形成有包含过渡金属氧化物的第一电阻变化层（2），在通孔内形成有包含过渡金属氧化物的第二电阻变化层（5），第一电阻变化层的电阻率与第二电阻变化层不同，第一电阻变化层和第二电阻变化层接触彼此仅在更靠近基板的通孔的开口（20）中。

10. 发明申请

US20100193760A1 CURRENT RESTRICTING ELEMENT, MEMORY APPARATUS INCORPORATING CURRENT RESTRICTING ELEMENT, AND FABRICATION METHOD THEREOF 有权
标题翻译：电流限制元件，包含电流限制元件的记忆装置及其制造方法
公开(公告)号：US20100193760A1
公开(公告)日：2010-08-05
申请号：US12669174
申请日：2008-07-11
申请人： Takeshi Takagi , Takumi Mikawa , Koji Arita , Mitsuteru Iijima , Takashi Okada
发明人： Takeshi Takagi , Takumi Mikawa , Koji Arita , Mitsuteru Iijima , Takashi Okada
IPC分类号： H01L45/00 , H01L27/04 , H01L21/02
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/24 , H01L45/00
摘要： In a current rectifying element (10), a barrier height φA of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height φB of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1
摘要翻译：在电流整流元件（10）中，阻挡层（11）在其厚度方向上的中心区域（14）的阻挡高度＆amp; A被夹在第一电极层（12）和第二电极层（13）之间）形成为大于阻挡层（11）和第一电极层（12）之间的界面（17）附近的区域和阻挡层（17）之间的界面（17）的势垒高度B （11）和第二电极层（13）。阻挡层（11）具有例如阻挡层（11a），（11b）和（11c）的三层结构。阻挡层（11a），（11b）和（11c）例如由SiNx2，SiNx1和SiNx1（X1

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