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    • 2. 发明授权
    • Semiconductor crystalline laminate structure, forming method of the
same, and semiconductor device employing the same
    • 半导体结晶层叠结构体及其形成方法以及使用其的半导体装置
    • US5495115A
    • 1996-02-27
    • US287276
    • 1994-08-08
    • Makoto KudoTomoyoshi MishimaTakuma TanimotoMisuzu Sagawa
    • Makoto KudoTomoyoshi MishimaTakuma TanimotoMisuzu Sagawa
    • H01L21/20H01L21/338H01L29/205H01L29/778H01L29/812H01S5/00H01S5/042
    • H01L29/7783H01L29/205
    • A semiconductor crystalline laminate structure wherein between a first semiconductor layer consisting of a first alloyed semiconductor and a second semiconductor layer which has an energy gap wider than that of the first alloyed semiconductor and a lattice constant smaller than that of the first alloyed semiconductor and consists of one semiconductor selected from a group of single-element semiconductor, compound semiconductor, and alloyed semiconductor which contain no semiconductor having a largest lattice constant among the semiconductor constituting the first alloyed semiconductor, a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of the first alloyed semiconductor and contains the semiconductor having a largest lattice constant among the semiconductors constituting the first alloyed semiconductor is formed in contact with these layers, a forming method for the semiconductor crystalline laminate structure, and a semiconductor device using the method are indicated.
    • 一种半导体结晶层叠结构,其中在由第一合金半导体构成的第一半导体层和具有比所述第一合金化半导体的能隙宽的能隙的第二半导体层之间,并且晶格常数小于所述第一合金化半导体的晶格常数,并且由 从构成第一合金化半导体的半导体中的不包含具有最大晶格常数的半导体的一组单元件半导体,化合物半导体和合金化半导体中选出的一个半导体,由具有能量的第二合金化半导体构成的第三半导体层 构成第一合金化半导体的半导体中具有最大晶格常数的半导体的间隙与这些层接触形成,半导体结晶层叠结构的形成方法和半导体结晶层叠结构 指示使用该方法的电感器件。