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1. 发明授权

US06395619B2 Process for fabricating a semiconductor device 有权
标题翻译：制造半导体器件的工艺
公开(公告)号：US06395619B2
公开(公告)日：2002-05-28
申请号：US09203330
申请日：1998-12-02
申请人： Takuji Tanigami , Kenji Hakozaki , Naoyuki Shinmura , Shinichi Sato , Masanori Yoshimi , Takayuki Taniguchi
发明人： Takuji Tanigami , Kenji Hakozaki , Naoyuki Shinmura , Shinichi Sato , Masanori Yoshimi , Takayuki Taniguchi
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： The present invention provides a process for fabricating semiconductor device comprising the steps of: forming an etching-stop layer on a semiconductor substrate; patterning the etching-stop layer so that the etching-stop layer remains in a region to be an active region and is removed from a region to be a device isolation region, followed by forming a trench in the region to be the device isolation region; depositing on the semiconductor substrate an insulating film having a thickness greater than or equal to the depth of the trench; forming a resist pattern having an opening above the etching-stop layer above the active region adjacent to a device isolation region whose width is greater than or equal to a predetermined value, followed by etching the insulating film using the resist pattern as a mask; and polishing the insulating film existing on the resulting semiconductor substrate for flattening after removing the resist pattern.
摘要翻译：本发明提供一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成蚀刻停止层; 图案化蚀刻停止层，使得蚀刻停止层保持在作为有源区的区域中，并从作为器件隔离区的区域去除，然后在该区域中形成作为器件隔离区的沟槽; 在半导体衬底上沉积厚度大于或等于沟槽深度的绝缘膜; 形成抗蚀剂图案，其具有在与宽度大于或等于预定值的器件隔离区相邻的有源区上方的蚀刻停止层上方的开口，然后使用抗蚀剂图案作为掩模蚀刻绝缘膜; 并且在除去抗蚀剂图案之后，对存在于所得半导体衬底上的绝缘膜进行抛光以使其变平。

2. 发明授权

US5708600A Method for writing multiple value into nonvolatile memory in an equal time 失效
标题翻译：在同一时间内将多个值写入非易失性存储器的方法
公开(公告)号：US5708600A
公开(公告)日：1998-01-13
申请号：US725661
申请日：1996-10-01
申请人： Kenji Hakozaki , Shinichi Sato , Takuji Tanigami
发明人： Kenji Hakozaki , Shinichi Sato , Takuji Tanigami
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02
CPC分类号： G11C11/5628 , G11C11/5621
摘要： There is provided a method for writing a multiple value into a nonvolatile memory capable of writing multiple value data into a floating gate type memory cell in an equal time even when the data are varied. With a specified voltage applied to a control gate of a memory cell, a drain voltage which is varied according to each of data values "11", "10" and "01" to a drain so that a write time required for setting a varied threshold voltage is equalized. By moving electrons between a floating gate and a drain through a gate insulating film, the threshold voltage of the memory cell is set.
摘要翻译：提供了一种用于将多值写入非易失性存储器的方法，该非易失性存储器能够在相等的时间内将多值数据写入浮置型存储单元，即使数据变化。利用施加到存储单元的控制栅极的指定电压，将漏极电压根据数据值“11”，“10”和“01”中的每一个变化到漏极，使得设置变化的所需的写入时间阈值电压相等。通过栅极绝缘膜在浮置栅极和漏极之间移动电子，设定存储单元的阈值电压。

3. 发明授权

US5742541A Writing method for nonvolatile semiconductor memory with soft-write repair for over-erased cells 失效
标题翻译：非易失性半导体存储器的写入方法，具有用于超擦除单元的软写修复
公开(公告)号：US5742541A
公开(公告)日：1998-04-21
申请号：US580515
申请日：1995-12-28
申请人： Takuji Tanigami , Shinichi Sato
发明人： Takuji Tanigami , Shinichi Sato
IPC分类号： G11C17/00 , G11C16/04 , G11C16/10 , G11C16/14 , G11C16/34
CPC分类号： G11C16/3409 , G11C16/0416 , G11C16/10 , G11C16/14 , G11C16/3404
摘要： A non-volatile semiconductor memory includes a plurality of memory cells. Each memory cell includes N-type source and drain regions formed in a P-well on a semiconductor substrate, a floating gate formed on the P-well with a tunnel oxide film therebetween, and a control gate formed on the floating gate with an interpoly dielectric film therebetween. The memory has a plurality of bit lines, a plurality of word lines and a source line. The source region of each memory cell is connected to the source line. The drain region of each memory cell is connected to one of the word lines. The memory cell is written to, erased, or read by selectively supplying suitable voltages to the source, bit, and word lines connected thereto. When a selected memory cell is written to by injection electrons into its floating gate, (1) a negative voltage is applied to the P-well and the source line, (2) a first positive voltage is applied to the selected bit line, (3) a second positive voltage is applied to the selected word line, and (4) OV is applied to the non-selected word line. The second positive voltage applied to the control gate is lower than a predetermined voltage between the source and the control gate.
摘要翻译：非易失性半导体存储器包括多个存储单元。每个存储单元包括形成在半导体衬底上的P阱中的N型源极和漏极区，在P阱上形成有在其间具有隧道氧化物膜的浮置栅极，以及在浮置栅极上形成的具有间隔电介质膜之间。存储器具有多个位线，多个字线和源极线。每个存储单元的源区连接到源极线。每个存储单元的漏极区域连接到一条字线。通过向连接到其的源，位和字线选择性地提供合适的电压来将存储单元写入，擦除或读取。当通过注入电子将选定的存储单元写入其浮动栅极时，（1）向P阱和源极线施加负电压，（2）将第一正电压施加到所选位线， 3）将第二正电压施加到所选字线，并且（4）将OV施加到未选择的字线。施加到控制栅极的第二正电压低于源极和控制栅极之间的预定电压。

4. 发明授权

US6069041A Process for manufacturing non-volatile semiconductor memory device by introducing nitrogen atoms 失效
标题翻译：通过引入氮原子制造非易失性半导体存储器件的方法
公开(公告)号：US6069041A
公开(公告)日：2000-05-30
申请号：US974158
申请日：1997-11-19
申请人： Takuji Tanigami , Shinichi Sato , Kenichi Azuma
发明人： Takuji Tanigami , Shinichi Sato , Kenichi Azuma
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28176 , H01L21/28273 , H01L29/511 , H01L29/518 , H01L21/28194 , Y10S438/91
摘要： A process for manufacturing a non-volatile semiconductor memory device by forming a tunnel dielectric film, a floating gate electrode, an interlayer capacitive film and a control gate electrode successively on a semiconductor substrate includes introducing nitrogen atoms into at least one of an interface between the floating gate electrode and the interlayer capacitive film and an interface between the interlayer capacitive film and the control gate electrode.
摘要翻译：通过在半导体衬底上依次形成隧道电介质膜，浮栅电极，层间电容膜和控制栅电极来制造非易失性半导体存储器件的工艺包括将氮原子引入至少一个浮栅电极和层间电容膜以及层间电容膜和控制栅电极之间的界面。

5. 发明授权

US6066531A Method for manufacturing semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US6066531A
公开(公告)日：2000-05-23
申请号：US99520
申请日：1998-06-18
申请人： Yukiharu Akiyama , Takuji Tanigami , Shinichi Sato
发明人： Yukiharu Akiyama , Takuji Tanigami , Shinichi Sato
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11521
摘要： A method for manufacturing a semiconductor memory device, including the steps of: forming a plurality of stripes comprising a first floating gate material film and a ion implantation protective film, covering one longitudinal side wall of the stripes with a resist pattern; removing a given width of the other side wall of the first floating gate material film by an isotropic etching in use of the resist pattern as a mask; forming an impurity region of low concentration by implanting impurity ions of a second conductivity type into the semiconductor substrate of the first conductivity type in use of the ion implantation protective film as a mask in a tilted direction after removing the resist pattern; and forming asymmetrical impurity regions on both sides of the stripe like first floating gate material film as viewed in the cross section along the direction perpendicular to the longitudinal direction of the stripes. According to the above-mentioned method, without using a side wall spacer, a semiconductor memory device provided with asymmetrical impurity regions having precisely desired forms can be obtained.
摘要翻译：一种制造半导体存储器件的方法，包括以下步骤：形成包括第一浮栅材料膜和离子注入保护膜的多个条，用抗蚀剂图案覆盖条的一个纵向侧壁; 通过使用抗蚀图案作为掩模，通过各向同性蚀刻去除第一浮栅材料膜的另一侧壁的给定宽度; 通过在去除抗蚀剂图案之后，在使用离子注入保护膜作为掩模作为掩模的情况下，将第二导电类型的杂质离子注入到第一导电类型的半导体衬底中，形成低浓度的杂质区; 以及沿着与条纹的纵向方向垂直的方向在横截面中看到的条状的第一浮栅材料膜的两侧上形成非对称杂质区域。根据上述方法，在不使用侧壁间隔物的情况下，可以获得具有精确期望形状的非对称杂质区域的半导体存储器件。

6. 发明授权

US06091632A Nonvolatile semiconductor storage device having a plurality of blocks of memory cell transistors formed on respective wells isolated from each other 失效
标题翻译：具有形成在彼此隔离的各个孔上的多个存储单元晶体块的非易失性半导体存储器件
公开(公告)号：US06091632A
公开(公告)日：2000-07-18
申请号：US66514
申请日：1998-04-24
申请人： Masanori Yoshimi , Shinichi Sato
发明人： Masanori Yoshimi , Shinichi Sato
IPC分类号： G11C16/02 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C16/3427 , H01L27/115
摘要： A plurality of blocks of memory cell transistors are formed on the respective isolated wells. In a write stage, a predetermined write-stage well voltage is applied to the well of a selected block including the memory cell transistors to be subjected to a write operation, a bias voltage is applied to the well of each of the remaining, non-selected blocks to increase a threshold voltage of the memory cell transistors of each non-selected block, in comparison with a threshold voltage determined by the predetermined write-stage well voltage, and a voltage is applied to the control gates of the memory cell transistors of each non-selected block to reduce a difference between a potential of the floating gate of each memory cell transistor of each non-selected block and a write-stage drain voltage applied to the drain of the memory cell transistor through the associated bit line such that a source-drain leak current of each memory cell transistor in the non-selected blocks falls in a permissible range.
摘要翻译：在各个隔离的阱上形成多个存储单元晶体管块。在写入阶段，将预定的写入阶段阱电压施加到包括要进行写入操作的存储单元晶体管的所选择的块的阱中，将偏置电压施加到剩余的非 - 与由预定写入级阱电压确定的阈值电压相比，增加每个未选择块的存储单元晶体管的阈值电压的选择块，并且将电压施加到存储单元晶体管的控制栅极每个未选择的块以减少每个未选择块的每个存储单元晶体管的浮置栅极的电位与通过相关联的位线施加到存储单元晶体管的漏极的写入级漏极电压之间的差异，使得未选择的块中的每个存储单元晶体管的源漏漏电流落在容许范围内。

7. 发明授权

US5962889A Nonvolatile semiconductor memory with a floating gate that has a bottom surface that is smaller than the upper surface 失效
标题翻译：具有浮动栅极的非易失性半导体存储器，其具有小于上表面的底表面
公开(公告)号：US5962889A
公开(公告)日：1999-10-05
申请号：US690621
申请日：1996-07-31
申请人： Yoshimitsu Yamauchi , Masanori Yoshimi , Shinichi Sato , Keizo Sakiyama
发明人： Yoshimitsu Yamauchi , Masanori Yoshimi , Shinichi Sato , Keizo Sakiyama
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： In the nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix of the present invention, the memory cell array includes: a semiconductor substrate; a tunnel oxide film formed on the semiconductor substrate; floating gates formed on the tunnel oxide film; first insulating films formed on the floating gates; and control gates formed on the first insulating films, wherein each of the floating gates includes a first polysilicon film and second polysilicon films, the second polysilicon films being formed on both sides of the first polysilicon film, second insulating films are formed on the tunnel oxide film between the first polysilicon films, the second insulating films having a predetermined thickness which is thinner than that of the first polysilicon films, and the second polysilicon films are formed on the second insulating films.
摘要翻译：在包括具有以本发明的矩阵排列的存储单元的存储单元阵列的非易失性半导体存储器中，存储单元阵列包括：半导体衬底; 形成在所述半导体基板上的隧道氧化膜; 在隧道氧化膜上形成浮栅; 在浮栅上形成的第一绝缘膜; 以及形成在所述第一绝缘膜上的控制栅极，其中每个所述浮置栅极包括第一多晶硅膜和第二多晶硅膜，所述第二多晶硅膜形成在所述第一多晶硅膜的两侧，所述第二绝缘膜形成在所述隧道氧化物上在第二绝缘膜上形成第一多晶硅膜之间的膜，具有比第一多晶硅膜薄的预定厚度的第二绝缘膜和第二多晶硅膜。

8. 发明授权

US08853579B2 Bearing mechanism for compact rotary member 有权
标题翻译：紧凑型旋转构件的轴承机构
公开(公告)号：US08853579B2
公开(公告)日：2014-10-07
申请号：US13978473
申请日：2012-04-26
申请人： Eijiro Shimoyama , Shinichi Sato , Noriyoshi Machida
发明人： Eijiro Shimoyama , Shinichi Sato , Noriyoshi Machida
IPC分类号： H01H3/04 , F16C35/00 , F16C35/02 , H01H13/14 , H01H3/46 , H01H3/32
CPC分类号： F16C35/02 , F16C33/20 , H01H3/46 , H01H13/14 , H01H2003/326
摘要： A bearing mechanism has a rotary member made of a resin, having a cylindrical bearing integrally formed thereof and protruding from a side surface of the rotary member; a base member made of a resin and rotatably supporting the rotary member, the base member having a support shaft protruding from a position facing the cylindrical bearing of the rotary member; and an urging member constantly urging the rotary member in a predetermined direction. The cylindrical bearing of the rotary member has a bearing hole to fit and insert the support shaft of the base member.
摘要翻译：轴承机构具有由树脂制成的旋转构件，其具有一体地形成并从旋转构件的侧表面突出的圆柱形轴承; 由树脂制成并可旋转地支撑所述旋转件的基座件，所述基座件具有从面向所述旋转件的圆柱形轴承的位置突出的支撑轴; 以及推动构件在预定方向上不断地推动旋转构件。旋转构件的圆柱形轴承具有用于装配和插入基座构件的支撑轴的轴承孔。

9. 发明授权

US08724284B2 Electrostatic protection component 有权
标题翻译：静电保护元件
公开(公告)号：US08724284B2
公开(公告)日：2014-05-13
申请号：US13475376
申请日：2012-05-18
申请人： Hidenobu Umeda , Makoto Yoshino , Takahiro Sato , Takuo Hattori , Shinichi Sato , Takeshi Shibayama
发明人： Hidenobu Umeda , Makoto Yoshino , Takahiro Sato , Takuo Hattori , Shinichi Sato , Takeshi Shibayama
IPC分类号： H01H47/00
CPC分类号： H05F3/04 , H01G4/40 , H01T2/00 , H01T4/12 , H05K9/0067 , H05K9/0079
摘要： An electrostatic protection component includes: a body in which a plurality of ceramic substrates is laminated; and a pair of discharge electrodes which are formed within the body and which are spaced to face each other. The discharge electrodes include main body portions extending along a longitudinal direction, and the main body portions include tips in the longitudinal direction and side edges extending along the longitudinal direction. The pair of discharge electrodes are arranged such that both the main body portions are adjacent to each other in a short direction. The discharge electrodes face each other in the short direction between the side edges, and discharge occurs only between the side edges, between the discharge electrodes.
摘要翻译：静电保护部件包括：层叠有多个陶瓷基板的主体; 以及一对放电电极，其形成在主体内并且彼此间隔开。放电电极包括沿着纵向方向延伸的主体部分，并且主体部分包括沿纵向方向的尖端和沿着纵向方向延伸的侧边缘。一对放电电极被布置成使得两个主体部分在短方向上彼此相邻。放电电极在侧边缘之间在短的方向上彼此面对，并且放电仅在放电电极之间的侧边缘之间发生。

10. 发明申请

US20130301962A1 BEARING MECHANISM FOR COMPACT ROTARY MEMBER 有权
标题翻译：紧凑型旋转轴承座机构
公开(公告)号：US20130301962A1
公开(公告)日：2013-11-14
申请号：US13978473
申请日：2012-04-26
申请人： Eijiro Shimoyama , Shinichi Sato , Noriyoshi Machida
发明人： Eijiro Shimoyama , Shinichi Sato , Noriyoshi Machida
IPC分类号： F16C35/02
CPC分类号： F16C35/02 , F16C33/20 , H01H3/46 , H01H13/14 , H01H2003/326
摘要： A bearing mechanism has a rotary member made of a resin, having a cylindrical bearing integrally formed thereof and protruding from a side surface of the rotary member; a base member made of a resin and rotatably supporting the rotary member, the base member having a support shaft protruding from a position facing the cylindrical bearing of the rotary member; and an urging member constantly urging the rotary member in a predetermined direction. The cylindrical bearing of the rotary member has a bearing hole to fit and insert the support shaft of the base member.
摘要翻译：轴承机构具有由树脂制成的旋转构件，其具有一体地形成并从旋转构件的侧表面突出的圆柱形轴承; 由树脂制成并可旋转地支撑所述旋转件的基座件，所述基座件具有从面向所述旋转件的圆柱形轴承的位置突出的支撑轴; 以及推动构件在预定方向上不断地推动旋转构件。旋转构件的圆柱形轴承具有用于装配和插入基座构件的支撑轴的轴承孔。

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