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1. 发明授权

US07710301B2 Digital/analog converter and transmitter for complex signals 失效
标题翻译：数字/模拟转换器和发射机用于复杂信号
公开(公告)号：US07710301B2
公开(公告)日：2010-05-04
申请号：US11755872
申请日：2007-05-31
申请人： Takeshi Ueno , Takafumi Yamaji
发明人： Takeshi Ueno , Takafumi Yamaji
IPC分类号： H03M1/66
CPC分类号： H03M1/662 , H04B1/0483 , H04B14/04
摘要： According to an embodiment of the invention, there is provided a digital/analog converter includes: a decoder that converts a (n−1)-phase input digital signal to a n-phase output digital signal; and a signal generating unit that generates analog signals according to the n-phase output digital signal.
摘要翻译：根据本发明的实施例，提供一种数字/模拟转换器，包括：将（n-1）相输入数字信号转换为n相输出数字信号的解码器; 以及根据n相输出数字信号产生模拟信号的信号产生单元。

2. 发明申请

US20080204298A1 AD CONVERTER AND RADIO RECEIVER 失效
标题翻译： AD转换器和无线接收器
公开(公告)号：US20080204298A1
公开(公告)日：2008-08-28
申请号：US12104488
申请日：2008-04-17
申请人： Takafumi Yamaji , Takeshi Ueno
发明人： Takafumi Yamaji , Takeshi Ueno
IPC分类号： H03M1/12
CPC分类号： H03M1/123 , H03M1/44 , H03M1/46
摘要： Disclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n≦m≦2n), a decoding part to generate m pieces of decoded analog signals from the m parallel pieces of quantized signals, and a residual amplifying part to output m pieces of amplified residual signals by multiplying respective differences between each of the m pieces of analog signals and each of the m pieces of decoded analog signals; a second conversion stage including a quantizing part to generate m parallel pieces of quantized signals from the m pieces of amplified residual signals; and a synthesizing part to generate m parallel pieces of digital signals by synthesizing each of the quantized signals in the first conversion stage and in the second conversion stage at each parallel position.
摘要翻译：公开了一种AD转换器，包括：第一转换级，包括量化部分，用于从表示n维向量（n <= m <= 2n）的m个输入模拟信号生成m个并行量化信号，生成 m个来自m个并行量化信号的解码模拟信号，以及残余放大部分，通过将m个模拟信号中的每一个与m个解码模拟信号中的每一个相乘来输出m个放大残差信号信号; 第二转换级，包括从所述m个放大残差信号中产生m个并行量化信号的量化部分; 以及通过在每个平行位置合成第一转换级和第二转换级中的每个量化信号来产生m个并行数字信号的合成部分。

3. 发明申请

US20060139191A1 D/A converter and communication apparatus 有权
公开(公告)号：US20060139191A1
公开(公告)日：2006-06-29
申请号：US11319106
申请日：2005-12-27
申请人： Akihide Sai , Takeshi Ueno , Takafumi Yamaji
发明人： Akihide Sai , Takeshi Ueno , Takafumi Yamaji
IPC分类号： H03M1/00
CPC分类号： H03M1/747
摘要： A D/A converter includes a plurality of current sources configured to be on or off according to input digital data; a constant voltage source configured to apply a constant voltage to the current sources; current supply wirings provided between the constant voltage source and the respective current source, the current supply wirings respectively having equal length from the constant voltage source to the respective current source; ground-side wirings summing up output currents from the plurality of current sources; and output terminals connected to the ground-side wirings, the output terminals outputting analogue data corresponding to the input digital data.

4. 发明申请

US20090245437A1 SAMPLE RATE CONVERTER AND RCEIVER USING THE SAME 审中-公开
标题翻译：采样速率变换器和RCEIVER使用相同
公开(公告)号：US20090245437A1
公开(公告)日：2009-10-01
申请号：US12369781
申请日：2009-02-12
申请人： Masanori FURUTA , Takafumi Yamaji , Takeshi Ueno
发明人： Masanori FURUTA , Takafumi Yamaji , Takeshi Ueno
IPC分类号： H04L27/06 , H03M7/00
CPC分类号： H03H17/0621 , H03H17/0282
摘要： A sample rate converter includes a multiplexer to select either one of an input signal and a first feedback signal, and to obtain a selected input signal, a decimator performing decimation on an Nth-order integration signal to generate an output signal, an interpolator performing interpolation on the output signal to generate a second feedback signal, a multiplier which multiplies the second feedback signal by a coefficient to generate a multiplication signal, a subtractor which subtracts the multiplication signal from the selected input signal to generate a residual signal, an adder which adds the residual signal to a third feedback signal to sequentially generate 1st-order to Nth-order integration signals, a register circuit configured to hold the integration signals, a multiplexer to select the first feedback signal from the integration signals that the register hold, and a multiplexer to select the third feedback signal from the integration signals that the register hold.
摘要翻译：采样率转换器包括多路复用器，用于选择输入信号和第一反馈信号中的任何一个，并获得所选择的输入信号;抽取器对N次积分信号执行抽取以产生输出信号;内插器执行插值在输出信号上产生第二反馈信号，乘法器，将第二反馈信号乘以系数以产生乘法信号;减法器，其从所选择的输入信号中减去乘法信号以产生残差信号;加法器，其将增加剩余信号到第三反馈信号以顺序地产生1阶到N阶积分信号，配置成保持积分信号的寄存器电路，多路复用器，从寄存器保持的积分信号中选择第一反馈信号，以及多路复用器从寄存器保持的积分信号中选择第三个反馈信号。

5. 发明授权

US07482959B2 D/A converter and communication apparatus 有权
标题翻译： D / A转换器和通信装置
公开(公告)号：US07482959B2
公开(公告)日：2009-01-27
申请号：US11319106
申请日：2005-12-27
申请人： Akihide Sai , Takeshi Ueno , Takafumi Yamaji
发明人： Akihide Sai , Takeshi Ueno , Takafumi Yamaji
IPC分类号： H03M1/66
CPC分类号： H03M1/747
摘要： A D/A converter includes a plurality of current sources configured to be on or off according to input digital data; a constant voltage source configured to apply a constant voltage to the current sources; current supply wirings provided between the constant voltage source and the respective current source, the current supply wirings respectively having equal length from the constant voltage source to the respective current source; ground-side wirings summing up output currents from the plurality of current sources; and output terminals connected to the ground-side wirings, the output terminals outputting analogue data corresponding to the input digital data.
摘要翻译： D / A转换器包括根据输入数字数据配置为开或关的多个电流源; 恒定电压源，被配置为向所述电流源施加恒定电压; 设置在恒压源和相应电流源之间的电流供应布线，电流源布线分别具有从恒定电压源到相应电流源的相等长度; 接地侧布线将来自多个电流源的输出电流相加; 和与地侧布线连接的输出端子，输出端子输出对应于输入数字数据的模拟数据。

6. 发明申请

US20090245429A1 SAMPLE RATE CONVERTER AND RECEIVER USING THE SAME 审中-公开
标题翻译：采样速率变换器和接收器
公开(公告)号：US20090245429A1
公开(公告)日：2009-10-01
申请号：US12399239
申请日：2009-03-06
申请人： Masanori FURUTA , Takafumi Yamaji , Takeshi Ueno
发明人： Masanori FURUTA , Takafumi Yamaji , Takeshi Ueno
IPC分类号： H04L27/06 , H04L7/00
CPC分类号： H03H17/0621 , H03H17/0664 , H03H2218/04 , H03H2218/06
摘要： A sample rate converter includes a multiplexer which multiplexes input signals, an interpolator which interpolates a multiplexed output signal to generate a first feedback signal, a multiplier which multiplies the first feedback signal by a coefficient, a subtracter which subtracts the multiplied signal from the multiplexed input signal, an adder which adds the residual signal and a second feedback signal to sequentially generate integrated signals corresponding to the input signals, respectively, a register circuit configured to individually hold integrated signals, a multiplexer which multiplexes the integrated signals from the register circuit to generate the second feedback signal, a multiplexer which multiplexes the integrated signals from the register circuit to generate a decimation target signal, a decimator which subjects the decimation target signal to decimation to generate the multiplexed output signal, and a discrimination circuit configured to discriminate the multiplexed output signal to generate output signals.
摘要翻译：采样率转换器包括多路复用输入信号的多路复用器，内插多路复用输出信号以产生第一反馈信号的内插器，将第一反馈信号乘以系数的乘法器，从多路复用输入中减去相乘的信号的减法器信号，加法器，其分别将残留信号和第二反馈信号分别顺序地产生与输入信号相对应的积分信号;配置为单独保持积分信号的寄存器电路;复用器，其将来自寄存器电路的积分信号多路复用以产生第二反馈信号，多路复用器，其对来自寄存器电路的积分信号进行多路复用以产生抽取目标信号;抽取目标信号抽取产生复用输出信号的抽取器;以及鉴别电路，输出信号产生输出信号。

7. 发明授权

US07532144B2 AD converter and radio receiver 失效
标题翻译： AD转换器和无线电接收器
公开(公告)号：US07532144B2
公开(公告)日：2009-05-12
申请号：US12104488
申请日：2008-04-17
申请人： Takafumi Yamaji , Takeshi Ueno
发明人： Takafumi Yamaji , Takeshi Ueno
IPC分类号： H03M1/12
CPC分类号： H03M1/123 , H03M1/44 , H03M1/46
摘要： Disclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n≦m≦2n), a decoding part to generate m pieces of decoded analog signals from the m parallel pieces of quantized signals, and a residual amplifying part to output m pieces of amplified residual signals by multiplying respective differences between each of the m pieces of analog signals and each of the m pieces of decoded analog signals; a second conversion stage including a quantizing part to generate m parallel pieces of quantized signals from the m pieces of amplified residual signals; and a synthesizing part to generate m parallel pieces of digital signals by synthesizing each of the quantized signals in the first conversion stage and in the second conversion stage at each parallel position.
摘要翻译：公开了一种AD转换器，包括：第一转换级，包括量化部分，用于从表示n维向量（n <= m <= 2n）的m个输入模拟信号生成m个并行量化信号，生成 m个来自m个并行量化信号的解码模拟信号，以及残余放大部分，通过将m个模拟信号中的每一个与m个解码模拟信号中的每一个相乘来输出m个放大残差信号信号; 第二转换级，包括从所述m个放大残差信号中产生m个并行量化信号的量化部分; 以及通过在每个平行位置合成第一转换级和第二转换级中的每个量化信号来产生m个并行数字信号的合成部分。

8. 发明申请

US20090079598A1 SAMPLE RATE CONVERTER 审中-公开
标题翻译：采样率转换器
公开(公告)号：US20090079598A1
公开(公告)日：2009-03-26
申请号：US12057647
申请日：2008-03-28
申请人： Masanori Furuta , Takafumi Yamaji , Takeshi Ueno
发明人： Masanori Furuta , Takafumi Yamaji , Takeshi Ueno
IPC分类号： H03M7/00
CPC分类号： H03H17/04 , H03H17/0416
摘要： The sample rate converter includes a synthesizing unit which synthesizes an input signal sampled with frequency fs with a feedback signal of the frequency fs, in a frequency band from 0 to fs/N (where N indicates a natural number), with a gain greater than at least 1, to generate a synthesized signal, a downsampler which downsamples the synthesized signal to obtain an output signal of sample rate fs/N, and an upsampler which upsamples the output signal to generate the feedback signal.
摘要翻译：采样率转换器包括合成单元，其将从频率fs采样的输入信号与频率fs的反馈信号在0至fs / N（其中N表示自然数）的频带中合成，增益大于至少1，以产生合成信号，下采样器，其对合成信号进行下采样以获得采样率fs / N的输出信号;以及上采样器，其对输出信号进行采样以产生反馈信号。

9. 发明授权

US07379009B2 AD converter and radio receiver 失效
标题翻译： AD转换器和无线电接收器
公开(公告)号：US07379009B2
公开(公告)日：2008-05-27
申请号：US11623803
申请日：2007-01-17
申请人： Takafumi Yamaji , Takeshi Ueno
发明人： Takafumi Yamaji , Takeshi Ueno
IPC分类号： H03M1/12
CPC分类号： H03M1/123 , H03M1/44 , H03M1/46
摘要： Disclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n
摘要翻译：公开了一种AD转换器，包括：第一转换级，包括量化部分，用于从表示n维向量（n

10. 发明申请

US20070011482A1 Clock generator, radio receiver using the same, function system, and sensing system 审中-公开
标题翻译：时钟发生器，使用相同的无线电接收器，功能系统和传感系统
公开(公告)号：US20070011482A1
公开(公告)日：2007-01-11
申请号：US11438589
申请日：2006-05-22
申请人： Akihide Sai , Takeshi Ueno , Takafumi Yamaji , Tetsuro Itakura
发明人： Akihide Sai , Takeshi Ueno , Takafumi Yamaji , Tetsuro Itakura
IPC分类号： G06F1/00
CPC分类号： H03L7/23 , H03L7/18
摘要： A clock generator having phase locked loops to receive reference signals from a shared reference signal source and generate clock signals differing in frequency, respectively, includes a phase comparator which generates a voltage signal in response to a phase difference between a phase of the reference signal and a phase of a feedback signal, a VCO controlled by a voltage signal from the phase comparator, and a frequency divider group connected in cascade in a feedback loop between an output of the VCO and an input of a feedback signal, and takes out a clock signals from each output of the frequency divider group.
摘要翻译：具有锁相环的时钟发生器分别接收来自共享参考信号源的参考信号并且分别产生频率不同的时钟信号，该相位比较器响应于参考信号的相位和相位差之间的相位差产生电压信号反馈信号的相位，由来自相位比较器的电压信号控制的VCO和在VCO的输出与反馈信号的输入之间的反馈回路中级联连接的分频器组，并且取出时钟来自分频器组的每个输出的信号。

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