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1. 发明授权

US4833395A Semiconductor device having a test circuit 失效
标题翻译：具有测试电路的半导体器件
公开(公告)号：US4833395A
公开(公告)日：1989-05-23
申请号：US111741
申请日：1987-10-23
申请人： Takeshi Sasaki , Hideo Monma
发明人： Takeshi Sasaki , Hideo Monma
IPC分类号： G01R31/28 , G01R31/3185 , G11C29/00
CPC分类号： G01R31/3185
摘要： A semiconductor device comprises a test signal generating circuit for generating a test signal having an arbitrary frequency, a first buffer for selectively outputting one of the test signal and an external input signal, at least one test circuit supplied with an output signal of the first buffer, an external output terminal, a logic circuit, a second buffer for selectively supplying to the external terminal one of the test signal from the test circuit and an output signal of the logic circuit, and a switching signal generating circuit for generating switching signals for the first and second buffers. The state of the test circuit is checked by use of the test signal to indirectly determine the state of the logic circuit.

2. 发明授权

US4703483A Chip on chip type integrated circuit device 失效
标题翻译：芯片片式集成电路器件
公开(公告)号：US4703483A
公开(公告)日：1987-10-27
申请号：US759448
申请日：1985-07-26
申请人： Yoshinori Enomoto , Hideo Monma , Shunzo Ohta , Takeshi Sasaki
发明人： Yoshinori Enomoto , Hideo Monma , Shunzo Ohta , Takeshi Sasaki
IPC分类号： G01R31/28 , G01R31/3185 , H01L25/065
CPC分类号： H01L25/0657 , G01R31/2853 , G01R31/318505 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2225/06596 , H01L2924/01078 , H01L2924/15153 , H01L2924/15165 , H01L2924/16195 , H01L2924/3011
摘要： A circuit for checking the integrity of interconnections between chips in a chip-on-chip type IC device is fabricated in respective portions on the lower and upper chips in peripheral areas thereof intermediate the inner logic circuit of each chip and the corresponding bonding pads. Selection circuits connected between the inner logic circuit signal terminals and the corresponding bonding pads of the chip are switched by control signals to be isolated and permit normal operation of the chip or to a checking mode to isolate the inner logic circuit and permit transmission of test signals through the interconnections. The test signals received through the interconnections are compared with the test signals as transmitted to determine the integrity of the individual interconnections. The disclosed apparatus and method provide for testing of the integrity of interconnections defining single direction signal paths of individual interconnections, as between the upper and lower chips, and for selectively bidirectional transmission through the individual interconnections.
摘要翻译：用于检查片上芯片型IC器件中的芯片之间的互连的完整性的电路是在每个芯片的内部逻辑电路和相应的焊盘之间的周边区域的下部和上部芯片的相应部分中制造的。连接在内部逻辑电路信号端子和芯片的相应接合焊盘之间的选择电路由要隔离的控制信号切换，并允许芯片的正常工作或检查模式以隔离内部逻辑电路并允许测试信号的传输通过互连。将通过互连接收的测试信号与传输的测试信号进行比较，以确定各个互连的完整性。所公开的装置和方法提供了确定单个互连的单向信号路径的互连的完整性的测试，如在上和下芯片之间以及通过各个互连的选择性双向传输。

3. 发明授权

US4280213A Quick feeding system for a counter 失效
标题翻译：快速送料系统为柜台
公开(公告)号：US4280213A
公开(公告)日：1981-07-21
申请号：US94435
申请日：1979-11-15
申请人： Masayuki Takahashi , Hideo Monma
发明人： Masayuki Takahashi , Hideo Monma
IPC分类号： G04G5/02 , H03K23/00 , G04C9/00
CPC分类号： G04G5/02
摘要： A quick feeding system for feeding quick counting pulses to a counter, such as an hours counter of an electronic clock of the digital display type, comprising frequency dividing circuits, a switch for effecting a quick feed of pulses to the counter and a quick feed pulse generation circuit connected between one of the frequency dividing circuits and the counter.
摘要翻译：用于将快速计数脉冲馈送到计数器的快速馈送系统，例如数字显示类型的电子时钟的小时计数器，包括分频电路，用于快速向计数器馈送脉冲的开关和快速进给脉冲连接在一个分频电路和计数器之间的发生电路。

4. 发明授权

US4692783A Gate array 失效
标题翻译：门阵列
公开(公告)号：US4692783A
公开(公告)日：1987-09-08
申请号：US922787
申请日：1986-10-23
申请人： Hideo Monma , Masato Ishiguro , Tetsuo Kawano
发明人： Hideo Monma , Masato Ishiguro , Tetsuo Kawano
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8238 , H01L27/04 , H01L27/092 , H01L27/118 , H01L29/78
CPC分类号： H01L27/11807 , H01L21/82
摘要： A gate array is disclosed having a plurality of basic cells each comprising a transistor whose gm is as low as one fifth to one twentieth that of the transistors in a conventional gate array. The low gm is provided by reducing the W/L ratio of the gate region of the transistor. The basic cell having the transistor of the low gm is formed to replace the conventional basic cell at a specified position in a specified basic cell array. The transistor of low gm reduces the number of basic cells necessary for forming a delay circuit, and elminates the need for an external resistance component which was formerly required when a pull-up or pull-down circuit or a monostable multivibrator was formed in the gate array.
摘要翻译：公开了具有多个基本单元的门阵列，每个基本单元包括其常规门阵列中的晶体管的gm低至五分之一至二十分之一的晶体管。通过降低晶体管的栅极区域的W / L比来提供低gm。具有低gm的晶体管的基本单元被形成为在指定的基本单元阵列中的指定位置处替换传统的基本单元。低gm的晶体管减少形成延迟电路所需的基本电池数量，并且最终需要一种外部电阻元件，这在先前在栅极中形成上拉或下拉电路或单稳态多谐振荡器时是需要的数组。

5. 发明授权

US4422038A Integrated circuit with frequency-dividing circuits capable of being tested at a high speed 失效
标题翻译：具有能够高速测试的分频电路的集成电路
公开(公告)号：US4422038A
公开(公告)日：1983-12-20
申请号：US237152
申请日：1981-02-18
申请人： Hideo Monma , Masayuki Takahashi , Masato Ishiguro
发明人： Hideo Monma , Masayuki Takahashi , Masato Ishiguro
IPC分类号： H03K21/40 , G04D7/12 , G04G99/00 , G01R31/28 , G01R23/00 , G04C3/00
CPC分类号： G04G99/00 , G04D7/12
摘要： An integrated circuit having a frequency-dividing circuit which can be tested at high speeds, in which the frequency-dividing circuit is separated into a first stage frequency-dividing circuit and a second stage frequency-dividing circuit, an output buffer circuit and a test signal input circuit are connected to an alarm terminal parallelly, and test signals applied to the alarm terminal are supplied to the second stage frequency-dividing circuit via the test signal input circuit and a switching circuit.
摘要翻译： PCT No.PCT / JP80 / 00138 Sec。 371日期1981年2月18日 102（e）日期1981年2月18日PCT Filed 1980年6月19日PCT公布。出版物WO80 / 02880 日期为1980年12月24日。具有分频电路的集成电路可以高速测试，其中分频电路分为第一级分频电路和第二级分频电路，输出缓冲电路和测试信号输入电路并联连接到报警端子，并且施加到报警端的测试信号经由测试信号输入电路和开关电路提供给第二级分频电路。

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