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1. 发明申请

US20130005137A1 BARRIER SEQUENCE FOR USE IN COPPER INTERCONNECT METALLIZATION 有权
标题翻译：用于铜相互连接金属化的栅栏序列
公开(公告)号：US20130005137A1
公开(公告)日：2013-01-03
申请号：US13609668
申请日：2012-09-11
申请人： Takeshi Nogami , Thomas M. Shaw , Andrew H. Simon , Jean E. Wynne , Chih-Chao Yang
发明人： Takeshi Nogami , Thomas M. Shaw , Andrew H. Simon , Jean E. Wynne , Chih-Chao Yang
IPC分类号： H01L21/768
CPC分类号： H01L23/53238 , H01L21/76844 , H01L21/76846 , H01L2924/0002 , H01L2924/00
摘要： A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.
摘要翻译：一种方法图形为多级集成电路结构的低K绝缘体层中的至少一个开口，使得铜导体在开口的底部露出。该方法然后在第一室中用第一钽氮化物层排列开口的侧壁和底部，并在第一室中的第一氮化钽层上形成钽层。接下来，在第一室中进行对开口的溅射蚀刻，以使开口底部的导体露出。在第一室中再次在导体，钽层和第一氮化钽层上形成第二钽氮化物层。在形成第二钽氮化物层之后，本文的方法在第二不同室中在第二氮化钽层上形成包含铂族金属的闪蒸层。

2. 发明申请

US20090179328A1 BARRIER SEQUENCE FOR USE IN COPPER INTERCONNECT METALLIZATION 审中-公开
标题翻译：用于铜相互连接金属化的栅栏序列
公开(公告)号：US20090179328A1
公开(公告)日：2009-07-16
申请号：US12013649
申请日：2008-01-14
申请人： Takeshi Nogami , Thomas M. Shaw , Andrew H. Simon , Jean E. Wynne , Chih-Chao Yang
发明人： Takeshi Nogami , Thomas M. Shaw , Andrew H. Simon , Jean E. Wynne , Chih-Chao Yang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76844 , H01L21/76846 , H01L2924/0002 , H01L2924/00
摘要： A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber. After this processing, the structure can be moved to a third chamber where copper is deposited on the flash layer in the opening until the opening is coated with copper in a third chamber.
摘要翻译：一种方法图形为多级集成电路结构的低K绝缘体层中的至少一个开口，使得铜导体在开口的底部露出。该方法然后在第一室中用第一钽氮化物层排列开口的侧壁和底部，并在第一室中的第一氮化钽层上形成钽层。接下来，在第一室中进行对开口的溅射蚀刻，以使开口底部的导体露出。在第一室中再次在导体，钽层和第一氮化钽层上形成第二钽氮化物层。在形成第二钽氮化物层之后，本文的方法在第二不同室中在第二氮化钽层上形成包含铂族金属的闪蒸层。在该处理之后，可以将结构移动到第三室，其中铜沉积在开口中的闪蒸层上，直到在第三室中用铜涂覆开口。

3. 发明授权

US08841212B2 Method of making a copper interconnect having a barrier liner of multiple metal layers 有权
标题翻译：制造具有多个金属层的阻挡衬里的铜互连的方法
公开(公告)号：US08841212B2
公开(公告)日：2014-09-23
申请号：US13609668
申请日：2012-09-11
申请人： Takeshi Nogami , Thomas M. Shaw , Andrew H. Simon , Jean E. Wynne , Chih-Chao Yang
发明人： Takeshi Nogami , Thomas M. Shaw , Andrew H. Simon , Jean E. Wynne , Chih-Chao Yang
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53238 , H01L21/76844 , H01L21/76846 , H01L2924/0002 , H01L2924/00
摘要： A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.
摘要翻译：一种方法图形为多级集成电路结构的低K绝缘体层中的至少一个开口，使得铜导体在开口的底部露出。该方法然后在第一室中用第一钽氮化物层排列开口的侧壁和底部，并在第一室中的第一氮化钽层上形成钽层。接下来，在第一室中进行对开口的溅射蚀刻，以使开口底部的导体露出。在第一室中再次在导体，钽层和第一氮化钽层上形成第二钽氮化物层。在形成第二钽氮化物层之后，本文的方法在第二不同室中在第二氮化钽层上形成包含铂族金属的闪蒸层。

4. 发明申请

US20090098728A1 STRUCTURE CU LINER FOR INTERCONNECTS USING A DOUBLE-BILAYER PROCESSING SCHEME 审中-公开
标题翻译：使用双BELAYER处理方案的互连结构CU LINER
公开(公告)号：US20090098728A1
公开(公告)日：2009-04-16
申请号：US11870649
申请日：2007-10-11
申请人： Stephan Grunow , Thomas McCarroll Shaw , Andrew H. Simon , Chih-Chao Yang , Tiblor Bolom , James Werking
发明人： Stephan Grunow , Thomas McCarroll Shaw , Andrew H. Simon , Chih-Chao Yang , Tiblor Bolom , James Werking
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , H01L21/76805 , H01L21/76865
摘要： The disclosed method forms a via between metallization layers in a semiconductor structure by patterning an insulator layer overlying a first metallization layer to include a via opening. The method lines the via opening with TaN and Ta liners and then sputter etches the via opening deeper through the TaN and Ta liners into the first metallization layer. After sputter etching, the method then lines the via opening with second TaN and Ta liners. Next, the method deposits a conductor into the via opening, thereby connecting the first and second metallization layers.
摘要翻译：所公开的方法通过图案化覆盖在第一金属化层上的绝缘体层以包括通孔开口在半导体结构中的金属化层之间形成通孔。该方法用TaN和Ta衬垫将通孔开口排列，然后通过TaN和Ta衬垫将通孔开口溅射到第一金属化层中。在溅射蚀刻之后，该方法然后将通孔与第二TaN和Ta衬垫分开。接下来，该方法将导体沉积到通孔开口中，从而连接第一和第二金属化层。

5. 发明申请

US20080160754A1 METHOD FOR FABRICATING A MICROELECTRONIC CONDUCTOR STRUCTURE 审中-公开
标题翻译：制造微电子导体结构的方法
公开(公告)号：US20080160754A1
公开(公告)日：2008-07-03
申请号：US11616532
申请日：2006-12-27
申请人： John A. Fitzsimmons , Stephan Grunow , Sanjay C. Mehta , Andrew H. Simon , Chih-Chao Yang
发明人： John A. Fitzsimmons , Stephan Grunow , Sanjay C. Mehta , Andrew H. Simon , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/02063 , H01L21/31144 , H01L21/76814
摘要： A method for fabricating a microelectronic structure includes forming a via aperture through a dielectric layer located over a substrate having a conductor layer therein, to expose the conductor layer. The conductor layer typically comprises a copper containing material. The method also includes etching the conductor layer to form a recessed conductor layer prior to etching a trench aperture within the dielectric layer. The trench aperture is typically contiguous with the via aperture to form a dual damascene aperture. By etching the conductor layer after forming the via aperture and before forming the trench aperture, such a dual damascene aperture is formed with enhanced dimensional integrity.
摘要翻译：一种制造微电子结构的方法包括：通过位于其中具有导体层的衬底上的电介质层形成通孔，以露出导体层。导体层通常包含含铜材料。该方法还包括在蚀刻介电层内的沟槽孔之前蚀刻导体层以形成凹陷的导体层。沟槽孔通常与通孔邻接以形成双镶嵌孔。通过在形成通孔之后蚀刻导体层，并且在形成沟槽孔之前，形成具有增强的尺寸完整性的这种双镶嵌孔。

6. 发明授权

US07241681B2 Bilayered metal hardmasks for use in dual damascene etch schemes 有权
标题翻译：用于双镶嵌蚀刻方案的双层金属硬掩模
公开(公告)号：US07241681B2
公开(公告)日：2007-07-10
申请号：US11330834
申请日：2006-01-12
申请人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas C. La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew H. Simon , Mark Hoinkis , Steffen K. Kaldor , Chih-Chao Yang
发明人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas C. La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew H. Simon , Mark Hoinkis , Steffen K. Kaldor , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76832 , H01L21/0332 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L2221/1036 , Y10T428/12576 , Y10T428/12806 , Y10T428/265 , Y10T428/31678
摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).
摘要翻译：用于制造半导体器件的双镶嵌工艺的金属硬掩模。金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

7. 发明申请

US20110108990A1 Capping of Copper Interconnect Lines in Integrated Circuit Devices 有权
标题翻译：集成电路器件中铜互连线的封盖
公开(公告)号：US20110108990A1
公开(公告)日：2011-05-12
申请号：US12613551
申请日：2009-11-06
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , David L. Rath , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , Chih-Chao Yang
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , David L. Rath , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , Chih-Chao Yang
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76849 , H01L21/76865 , H01L2924/0002 , H01L2924/00
摘要： A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.
摘要翻译：一种封盖线的方法包括通过选择性沉积工艺在铜线上形成金属膜层，铜线设置在电介质基底中，其中沉积还导致杂散金属材料沉积在介质基片的表面上，并用各向同性蚀刻工艺进行蚀刻以除去电介质基底表面上的金属膜层和杂散金属材料的一部分，其中金属膜层以足以使金属膜层盖保持在其上的初始厚度沉积铜线除去杂散金属材料。

8. 发明授权

US08298948B2 Capping of copper interconnect lines in integrated circuit devices 有权
标题翻译：在集成电路器件中封装铜互连线
公开(公告)号：US08298948B2
公开(公告)日：2012-10-30
申请号：US12613551
申请日：2009-11-06
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , David L. Rath , Sujatha Sankaran , Andrew H. Simon , Theodorus Eduardus Standaert , Chih-Chao Yang
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , David L. Rath , Sujatha Sankaran , Andrew H. Simon , Theodorus Eduardus Standaert , Chih-Chao Yang
IPC分类号： H01L21/44 , H01L21/302
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76849 , H01L21/76865 , H01L2924/0002 , H01L2924/00
摘要： A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.
摘要翻译：一种封盖线的方法包括通过选择性沉积工艺在铜线上形成金属膜层，铜线设置在电介质基底中，其中沉积还导致杂散金属材料沉积在介质基片的表面上，并用各向同性蚀刻工艺进行蚀刻以除去电介质基底表面上的金属膜层和杂散金属材料的一部分，其中金属膜层以足以使金属膜层盖保持在其上的初始厚度沉积铜线除去杂散金属材料。

9. 发明授权

US07494915B2 Back end interconnect with a shaped interface 失效
标题翻译：后端互连与成形接口
公开(公告)号：US07494915B2
公开(公告)日：2009-02-24
申请号：US11463447
申请日：2006-08-09
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.
摘要翻译：在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

10. 发明授权

US07122462B2 Back end interconnect with a shaped interface 有权
公开(公告)号：US07122462B2
公开(公告)日：2006-10-17
申请号：US10707122
申请日：2003-11-21
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

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