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1. 发明授权

US4542164A Flame-retardant polyolefin foam 失效
标题翻译：阻燃聚烯烃泡沫
公开(公告)号：US4542164A
公开(公告)日：1985-09-17
申请号：US538921
申请日：1983-10-04
申请人： Takeshi Nishioka , Akira Nakamura , Kenji Yabe
发明人： Takeshi Nishioka , Akira Nakamura , Kenji Yabe
IPC分类号： C08J9/00 , C08L23/02 , C08J9/10
CPC分类号： C08J9/0061 , C08L23/02 , C08J2323/02 , C08J2463/00 , Y10S521/907
摘要： The present invention relates to a flame-retardant polyolefin foam comprising a polyolefinic thermoplastic resin consisting mainly of a homopolymer of .alpha.-olefin or copolymer of .alpha.-olefins having 2 to 10 carbon atoms; 2 to 10 percent by weight as bromine content, based on the weight of the foam, of a bisphenol A-based brominated epoxy resin or a crosslinked product thereof; and 0 to 25 percent by weight, based on the weight of the foam, of an inorganic filler. The foam of the present invention has superior flame retardancy and thermoformability in addition to the superior heat insulating property and shock absorbing property of the polyolefin foam, and because of these superior characteristics it is useful as an automotive interior material, etc.
摘要翻译：本发明涉及一种阻燃聚烯烃泡沫体，其包含主要由α-烯烃均聚物或具有2-10个碳原子的α-烯烃共聚物组成的聚烯烃热塑性树脂; 2重量％至10重量％的溴含量，基于泡沫的重量，双酚A型溴化环氧树脂或其交联产物; 和基于泡沫重量的0至25重量％的无机填料。本发明的泡沫体除了具有优异的聚烯烃泡沫的隔热性和冲击吸收性外，还具有优异的阻燃性和热成型性，并且由于这些优异的特性，作为汽车内饰材料等是有用的。

2. 发明申请

US20110217906A1 POLISHING APPARATUS AND POLISHING METHOD 有权
标题翻译：抛光装置和抛光方法
公开(公告)号：US20110217906A1
公开(公告)日：2011-09-08
申请号：US13036114
申请日：2011-02-28
申请人： Masayuki NAKANISHI , Tetsuji Togawa , Kenya Ito , Masaya Seki , Kenji Iwade , Takeo Kubota , Takeshi Nishioka
发明人： Masayuki NAKANISHI , Tetsuji Togawa , Kenya Ito , Masaya Seki , Kenji Iwade , Takeo Kubota , Takeshi Nishioka
IPC分类号： B24B1/00 , B24B55/00
CPC分类号： B24B1/00 , B24B55/00
摘要： A polishing apparatus can effectively prevent abrasive particles from falling off a polishing tape during polishing. The polishing apparatus includes: a polishing head for polishing a peripheral portion of a substrate by pressing a surface of a polishing tape, having abrasive particles fixed on the surface, against the peripheral portion of the substrate while allowing the polishing tape to travel in one direction; and a conditioning apparatus, disposed upstream of the polishing head in the traveling direction of the polishing tape, for conditioning the surface of the polishing tape in advance in order to prevent the abrasive particles from falling off the surface of the polishing tape during polishing.
摘要翻译：抛光装置可以有效地防止研磨颗粒在抛光过程中从抛光带上脱落。抛光装置包括：抛光头，用于通过将具有固定在表面上的研磨颗粒的研磨带的表面按压在基板的周边部分上，同时允许研磨带沿单向移动来抛光基板的周边部分 ; 以及调整装置，其设置在研磨带的行进方向上的抛光头的上游，用于预先调整研磨带的表面，以防止研磨颗粒在抛光期间从研磨带的表面脱落。

3. 发明授权

US07996813B2 Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program 有权
标题翻译：用于生成图案的方法，制造半导体器件的方法，半导体器件和计算机程序
公开(公告)号：US07996813B2
公开(公告)日：2011-08-09
申请号：US12654865
申请日：2010-01-07
申请人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
发明人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
IPC分类号： G06F15/04
CPC分类号： G06F17/5068
摘要： A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
摘要翻译：一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。

4. 发明申请

US20050167842A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050167842A1
公开(公告)日：2005-08-04
申请号：US10974922
申请日：2004-10-28
申请人： Naofumi Nakamura , Noriaki Matsunaga , Sachiyo Ito , Masahiko Hasunuma , Takeshi Nishioka
发明人： Naofumi Nakamura , Noriaki Matsunaga , Sachiyo Ito , Masahiko Hasunuma , Takeshi Nishioka
IPC分类号： H01L23/52 , H01L21/00 , H01L21/3205 , H01L21/822 , H01L23/00 , H01L23/522 , H01L23/58 , H01L27/04 , H01L27/10 , H01L29/40
CPC分类号： H01L23/564 , H01L23/522 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first insulating layer provided above a semiconductor substrate. The first insulating layer includes a layer consisting essentially of a material having a relative dielectric constant smaller than 3. The first insulating layer includes a first integral structure consisting of a plug and wiring. The upper surface of the wiring is flush with the upper surface of the first insulating layer, and the lower surface of the plug is flush with the lower surface of the first insulating layer. A region protective member is formed of a second integral structure consisting of a plug and wiring. The second integral structure extends from the upper surface of the first insulating layer to the lower surface of the first insulating layer. The region protective member surrounds one of first to n-th regions (n being a natural 2 or more) partitioned by a boundary region on a horizontal plane.
摘要翻译：半导体器件包括设置在半导体衬底之上的第一绝缘层。第一绝缘层包括基本上由相对介电常数小于3的材料组成的层。第一绝缘层包括由插头和布线组成的第一整体结构。布线的上表面与第一绝缘层的上表面齐平，插头的下表面与第一绝缘层的下表面齐平。区域保护构件由由插头和布线组成的第二整体结构形成。第二整体结构从第一绝缘层的上表面延伸到第一绝缘层的下表面。区域保护构件围绕由水平面上的边界区划分的第一至第n区域（n为自然2以上）中的一个。

5. 发明授权

US08492276B2 Chemical mechanical polishing aqueous dispersion and chemical mechanical polishing method 有权
标题翻译：化学机械抛光水性分散体和化学机械抛光方法
公开(公告)号：US08492276B2
公开(公告)日：2013-07-23
申请号：US12537766
申请日：2009-08-07
申请人： Taichi Abe , Hirotaka Shida , Akihiro Takemura , Mitsuru Meno , Shinichi Hirasawa , Kenji Iwade , Takeshi Nishioka
发明人： Taichi Abe , Hirotaka Shida , Akihiro Takemura , Mitsuru Meno , Shinichi Hirasawa , Kenji Iwade , Takeshi Nishioka
IPC分类号： H01L21/3212
CPC分类号： C09K13/06 , C09K3/1463 , H01L21/3212 , H01L21/7684
摘要： A chemical mechanical polishing aqueous dispersion is used to polish a polishing target that includes an interconnect layer that contains tungsten. The chemical mechanical polishing aqueous dispersion includes: (A) a cationic water-soluble polymer; (B) an iron (III) compound; and (C) colloidal silica particles. The content (MA) (mass %) of the cationic water-soluble polymer (A) and the content (MB) (mass %) of the iron (III) compound (B) satisfy the relationship “MA/MB=0.004 to 0.1”. The chemical mechanical polishing aqueous dispersion has a pH of 1 to 3.
摘要翻译：使用化学机械抛光水性分散体来抛光包括含有钨的互连层的抛光对象。化学机械抛光水分散体包括：（A）阳离子水溶性聚合物; （B）铁（III）化合物; 和（C）胶体二氧化硅颗粒。阳离子水溶性聚合物（A）的含量（质量％）（质量％）和铁（III）化合物（B）的含量（MB）（质量％）满足关系式“MA / MB = 0.004〜0.1 “。化学机械抛光水性分散体的pH为1〜3。

6. 发明授权

US07985685B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07985685B2
公开(公告)日：2011-07-26
申请号：US12262439
申请日：2008-10-31
申请人： Yukiteru Matsui , Masako Kinoshita , Seiro Miyoshi , Yoshikuni Tateyama , Takeshi Nishioka , Hiroyuki Yano
发明人： Yukiteru Matsui , Masako Kinoshita , Seiro Miyoshi , Yoshikuni Tateyama , Takeshi Nishioka , Hiroyuki Yano
IPC分类号： H01L21/311
CPC分类号： H01L21/02118 , C09G1/02 , H01L21/022 , H01L21/02282 , H01L21/31058 , H01L21/31144 , H01L21/312 , H01L21/76808 , H01L21/76811 , H01L21/76835
摘要： A method for manufacturing a semiconductor device is provided, the method includes forming a coated film by coating a solution containing a solvent and an organic component above an insulating film located above a semiconductor substrate and having a recess, baking the coated film at a first temperature which does not accomplish cross-linking of the organic component to obtain an organic film precursor, polishing the organic film precursor using a slurry containing resin particles to leave the organic film precursor in the recess, baking the left organic film precursor at a second temperature which is higher than the first temperature to remove the solvent to obtain a first organic film embedded in the recess, forming a second organic film on the insulating film, thereby obtaining an underlying film, forming an intermediate layer and a resist film successively above the underlying film, and subjecting the resist film to patterning exposure.
摘要翻译：提供了一种制造半导体器件的方法，该方法包括通过将含有溶剂和有机组分的溶液涂覆在位于半导体衬底上方并具有凹槽的绝缘膜上的溶液形成涂覆膜，在第一温度下烘烤该涂膜其不能实现有机成分的交联以获得有机膜前体，使用含有树脂颗粒的浆料将有机膜前体抛光以在凹槽中离开有机膜前体，在第二温度下烘烤左有机膜前体高于第一温度以除去溶剂以获得嵌入在凹部中的第一有机膜，在绝缘膜上形成第二有机膜，从而获得下面的膜，在基底膜上连续形成中间层和抗蚀剂膜并对抗蚀剂膜进行图案曝光。

7. 发明授权

US07339256B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07339256B2
公开(公告)日：2008-03-04
申请号：US10974922
申请日：2004-10-28
申请人： Naofumi Nakamura , Noriaki Matsunaga , Sachiyo Ito , Masahiko Hasunuma , Takeshi Nishioka
发明人： Naofumi Nakamura , Noriaki Matsunaga , Sachiyo Ito , Masahiko Hasunuma , Takeshi Nishioka
IPC分类号： H01L29/72
CPC分类号： H01L23/564 , H01L23/522 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first insulating layer provided above a semiconductor substrate. The first insulating layer includes a layer consisting essentially of a material having a relative dielectric constant smaller than 3. The first insulating layer includes a first integral structure consisting of a plug and wiring. The upper surface of the wiring is flush with the upper surface of the first insulating layer, and the lower surface of the plug is flush with the lower surface of the first insulating layer. A region protective member is formed of a second integral structure consisting of a plug and wiring. The second integral structure extends from the upper surface of the first insulating layer to the lower surface of the first insulating layer. The region protective member surrounds one of first to n-th regions (n being a natural 2 or more) partitioned by a boundary region on a horizontal plane.
摘要翻译：半导体器件包括设置在半导体衬底之上的第一绝缘层。第一绝缘层包括基本上由相对介电常数小于3的材料组成的层。第一绝缘层包括由插头和布线组成的第一整体结构。布线的上表面与第一绝缘层的上表面齐平，插头的下表面与第一绝缘层的下表面齐平。区域保护构件由由插头和布线组成的第二整体结构形成。第二整体结构从第一绝缘层的上表面延伸到第一绝缘层的下表面。区域保护构件围绕由水平面上的边界区划分的第一至第n区域（n为自然2以上）中的一个。

8. 发明授权

US5664989A Polishing pad, polishing apparatus and polishing method 失效
标题翻译：抛光垫，抛光装置和抛光方法
公开(公告)号：US5664989A
公开(公告)日：1997-09-09
申请号：US683265
申请日：1996-07-18
申请人： Rempei Nakata , Hisashi Kaneko , Nobuo Hayasaka , Takeshi Nishioka , Yoshikuni Tateyama , Yutaka Nakano , Yasutaka Sasaki
发明人： Rempei Nakata , Hisashi Kaneko , Nobuo Hayasaka , Takeshi Nishioka , Yoshikuni Tateyama , Yutaka Nakano , Yasutaka Sasaki
IPC分类号： B24B37/20 , B24B37/22 , B24B37/24 , B24D13/14 , C08J5/14 , H01L21/304 , B24B1/00
CPC分类号： B24B37/22
摘要： A polishing pad comprises at least a first layer having a first main surface serving to polish a substrate to be polished and a second main surface, and a second layer positioned to face the second main surface of the first layer and having fine bags arranged therein, fluid being hermetically sealed in the fine bag.
摘要翻译：抛光垫至少包括具有用于抛光待抛光基板的第一主表面和第二主表面的第一层，以及设置成面对第一层的第二主表面并且具有布置在其中的细小袋的第二层，流体密封在细袋中。

9. 发明授权

US5402485A Two-wire termination impedance generation circuit of subscriber circuit 失效
标题翻译：用户电路的二线终端阻抗产生电路
公开(公告)号：US5402485A
公开(公告)日：1995-03-28
申请号：US189412
申请日：1994-01-31
申请人： Kenji Takato , Kazuhiro Yoshida , Kazuyuki Minohara , Yoshinobu Imai , Takeshi Nishioka
发明人： Kenji Takato , Kazuhiro Yoshida , Kazuyuki Minohara , Yoshinobu Imai , Takeshi Nishioka
IPC分类号： H04Q3/42 , H04M3/00 , H04M19/00 , H04M1/76
CPC分类号： H04M3/005 , H04M19/005
摘要： A two-wire termination impedance generation circuit of a subscriber circuit including differential amplifiers, which is provided with a network circuit including capacitors and resistors, an input point, and current sources, the capacitor being comprised of series connected first and second capacitors, the resistor being comprised of series connected first and second resistors and having a high band bypass capacitor connected at the intermediate connecting point of the same, and the resistor being comprised of a complex termination resistor forming an internal termination impedance and a series connected complex termination resistor and complex termination capacitor being connected directly to the telephone line as an external termination impedance, wherein the frequency characteristics can be improved in three ways.
摘要翻译：一种包括差分放大器的用户电路的二线终端阻抗产生电路，其具有包括电容器和电阻器的网络电路，输入点和电流源，所述电容器由串联连接的第一和第二电容器组成，所述电阻器由串联连接的第一和第二电阻器组成，并具有连接在其中间连接点处的高频带旁路电容器，并且该电阻器由形成内部终端阻抗的复合终端电阻器和串联连接的复合终端电阻器和复合体组成终端电容器直接连接到电话线作为外部终端阻抗，其中可以三种方式改善频率特性。

10. 发明授权

US4587071A Production of polyethylene terephthalate film for magnetic recording 失效
标题翻译：用于磁记录的聚对苯二甲酸乙二醇酯薄膜
公开(公告)号：US4587071A
公开(公告)日：1986-05-06
申请号：US748295
申请日：1985-06-24
申请人： Satoyuki Minami , Kazuhiro Tanaka , Takeshi Nishioka
发明人： Satoyuki Minami , Kazuhiro Tanaka , Takeshi Nishioka
IPC分类号： B29C55/00 , B29C55/06 , B29C55/14 , B29C55/16 , C08J5/18 , G11B5/73
CPC分类号： C08J5/18 , B29C55/005 , B29C55/065 , B29C55/143 , B29C55/16 , G11B5/7305 , B29K2067/00 , C08J2367/02 , Y10S428/90 , Y10S428/91 , Y10T428/263 , Y10T428/264 , Y10T428/265 , Y10T428/31786
摘要： The present invention relates to a polyethylene terephthalate film having the sum of F-5 values in longitudinal and transverse directions of 3500 to 5000 kg/cm.sup.2, absolute heat shrinkages in longitudinal and transverse directions at 100.degree. C. of up to 2.5% and amorphous orientation factor of -1.5 to 0.5, a process for the production thereof and a magnetic recording medium containing the film as a base. The polyethylene terephthalate film useful as a magnetic recording medium having super high-tensile-strength in both longitudinal and transverse directions and a low heat shrinkage is provided, while it has been considered that such properties could not be obtained in polyethylene terephthalate film.

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