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1. 发明授权

US6079816A Electrostatic image forming apparatus having control electrode protection means 失效
标题翻译：具有控制电极保护装置的静电图像形成装置
公开(公告)号：US6079816A
公开(公告)日：2000-06-27
申请号：US21159
申请日：1998-02-10
申请人： Takeshi Nakamura , Hironori Ogasawara , Nobuhiko Nakano , Hiroshi Kuranaga
发明人： Takeshi Nakamura , Hironori Ogasawara , Nobuhiko Nakano , Hiroshi Kuranaga
IPC分类号： B41J2/385 , B41J2/415 , B41J29/02 , G03G15/05 , G03G15/34 , G03G21/16 , B41J2/06
CPC分类号： G03G21/1652 , B41J2/4155 , B41J29/02 , G03G15/346 , G03G21/1633 , G03G2221/169
摘要： An image forming apparatus includes an opening and closing member mounted to an apparatus main body so that it can be open and closed, and a head cover for protecting the surface of a control electrode when opening the opening and closing member without disturbing an operation of controlling the flying of a toner by the control electrode in a closed state of the opening and closing member as being moved interlocking with opening and closing operations of the opening and closing member. According to the described arrangement, when the opening and closing member is open to remove a jammed sheet, exchange a toner cartridge, carry out various checking for printing inferior or install and remove a unit including the control electrode with respect to the apparatus main body, the control electrode which would be exposed otherwise can be prevented from being touched with an operator's finger or other member of the apparatus, etc.
摘要翻译：一种图像形成装置，包括安装在设备主体上以使其能够打开和关闭的打开和关闭部件;以及头盖，用于在打开打开和关闭部件时保护控制电极的表面，而不会干扰控制的操作在打开和关闭构件的打开和关闭操作中与控制电极在打开和关闭构件的关闭状态下的调色剂飞行互动。根据上述结构，当打开和关闭构件打开以取出卡住的纸张时，更换调色剂盒，进行各种打印检查，或者相对于设备主体安装和移除包括控制电极的单元，可以防止另外暴露的控制电极与操作者的手指或设备的其他部件等碰撞。

2. 发明授权

US5408661A Communication processor 失效
标题翻译：通讯处理器
公开(公告)号：US5408661A
公开(公告)日：1995-04-18
申请号：US906719
申请日：1992-06-30
申请人： Hiroshi Kuranaga
发明人： Hiroshi Kuranaga
IPC分类号： G06F13/00 , G06F13/12 , H04L29/06 , H04L29/10 , H04Q11/04
CPC分类号： H04Q11/0457 , G06F13/128 , H04L29/06 , H04Q2213/05 , H04Q2213/055 , H04Q2213/056 , H04Q2213/103
摘要： Data received from a first layer is processed in a communication processor. Memory controller determines whether or not an instruction to be processed next by a processing circuit is stored in an internal RAM. When it is stored, it reads the instruction from internal RAM, and otherwise, it reads an instruction from an external ROM through an DMAC. Processing circuit changes setting of register values in respective registers in memory controller to values of the corresponding layer, when processing for one layer is completed. Consequently, the layer to be processed by the communication processor is switched.
摘要翻译：在通信处理器中处理从第一层接收的数据。存储器控制器确定处理电路接下来要处理的指令是否存储在内部RAM中。存储时，从内部RAM读取指令，否则通过DMAC从外部ROM读取指令。当一层的处理完成时，处理电路将存储器控制器中相应寄存器中的寄存器值的设置改变为相应层的值。因此，切换由通信处理器处理的层。

3. 发明授权

US4876466A Programmable logic array having a changeable logic structure 失效
标题翻译：具有可变逻辑结构的可编程逻辑阵列
公开(公告)号：US4876466A
公开(公告)日：1989-10-24
申请号：US269763
申请日：1988-11-10
申请人： Harufusa Kondou , Hiroshi Kuranaga
发明人： Harufusa Kondou , Hiroshi Kuranaga
IPC分类号： H01L27/112 , H03K3/356 , H03K19/177
CPC分类号： H03K3/356052 , H01L27/112 , H03K19/17712
摘要： Programmable Logic Array PLA) cells are arranged at intersections of input lines and output lines of the array. Particular PLA cells to be programmed are arbitrarily selected by word line and bit line decoders. Switches for programming the PLA cells to implement a desired logic function are controlled by data stored in a random access memory whereby programming of the PLA can be changed arbitrarily and during operation of a system including the PLA.
摘要翻译：可编程逻辑阵列PLA）单元布置在阵列的输入线和输出线的交点处。要编程的特定PLA单元由字线和位线解码器任意选择。用于编程PLA单元以实现期望的逻辑功能的开关由存储在随机存取存储器中的数据控制，从而可以任意地改变PLA的编程，并且在包括PLA的系统的操作期间。

4. 发明授权

US5602706A Double-cassette-type magnetic recording-reproduction apparatus 失效
标题翻译：双盒式磁记录再生装置
公开(公告)号：US5602706A
公开(公告)日：1997-02-11
申请号：US431411
申请日：1995-04-28
申请人： Hiroshi Kuranaga , Hiroshi Furuhara
发明人： Hiroshi Kuranaga , Hiroshi Furuhara
IPC分类号： G11B15/26 , G11B15/00 , G11B15/10 , G11B15/18 , G11B5/008 , G11B15/68 , G11B17/00
CPC分类号： G11B15/00 , G11B15/103 , G11B15/1883
摘要： A double-cassette-type magnetic recording-reproduction apparatus wherein a cam gear allows the second over-stroke lever to shift in advancing and retracting manners and, following these movements, a mode lever and the second head mount are allowed to move to the first through third positions. When the mode lever is located at the first position, the first over-stroke lever is shifted to an operable position and the second head mount is blocked by the second idler lever from its advancing movement. When the mode lever is located at the second position, the shift-blocking state of the second head mount is released, and the first over-stroke lever is not allowed to shift. When the mode lever is located at the third position, the first over-stroke lever and the second head mount are allowed to shift to the operable positions. This construction makes it possible to reduce the number of driving means and cut the cost of production.
摘要翻译：一种双盒式磁记录再现装置，其中凸轮齿轮允许第二过冲程控制杆在前进和后退方式上移动，并且在这些移动之后，模式杆和第二头架被允许移动到第一通过第三职位。当模式杆位于第一位置时，第一超行程杆被移动到可操作位置，并且第二头架被第二惰轮杆阻挡其前进运动。当模式杆位于第二位置时，第二头架的挡挡状态被解除，第一超行程杆不允许偏移。当模式杆位于第三位置时，允许第一超行程杆和第二头座移动到可操作位置。这种结构使得可以减少驱动装置的数量并降低生产成本。

5. 发明授权

US06480235B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06480235B1
公开(公告)日：2002-11-12
申请号：US09521459
申请日：2000-03-08
申请人： Satoshi Sugawa , Hiroshi Kuranaga
发明人： Satoshi Sugawa , Hiroshi Kuranaga
IPC分类号： H04N327
CPC分类号： H04N5/46
摘要： A plurality of frames constituting a screen are divided into a plurality of groups such as G1 through G4. The number of pixels per line is made different between any adjacent two of these groups in such a manner that all lines included in each group will have the same number of pixels each. There should be a plurality of groups such as G2 through G4 which exclude lines having active pixels corresponding to image portions. Lines 1 through 480 having active pixels may have the same number of pixels each. The number of pixels per line is allowed to be different by 1 between any adjacent two of the groups.
摘要翻译：构成屏幕的多个帧被分成多个组，例如G1至G4。在每个组中的任何相邻的两个组之间的每个像素的像素数量不同，使得包括在每个组中的所有行将具有相同数量的像素。应该存在多个诸如G2至G4的组，排除具有对应于图像部分的有源像素的行。具有活动像素的行1至480可以具有相同数量的像素。每行的像素数允许在任何相邻的两个组之间变化1。

6. 发明授权

US5148430A Transmitter/receiver for generating transmitting data signal in synchronization with received data signal 失效
标题翻译：用于与接收的数据信号同步地生成发送数据信号的发送器/接收器
公开(公告)号：US5148430A
公开(公告)日：1992-09-15
申请号：US660825
申请日：1991-02-26
申请人： Hiroshi Kuranaga , Kouji Gotou
发明人： Hiroshi Kuranaga , Kouji Gotou
IPC分类号： H04L7/00 , H04L7/033
CPC分类号： H04L7/0331
摘要： A transmitter/receiver applicable as an interface circuit in ISDN terminals is disclosed. In externally designated total phase deviation measurement mode, the delay time caused by a receiver circuit and a driver circuit, i.e. a phase difference, is predetected by a phase comparator. The detected phase difference signal is stored in a phase control circuit, and the phase control circuit controls the pahse of a periodical timing signal generated from a PLL circuit. Therefore, as a data buffer applies a transmitting data to the driver circuit 7 in response to the phase control timing signal, the phase difference of the transmitting data signal generated from the driver circuit relative to the received data signal is made to be the minimum.
摘要翻译：公开了适用于ISDN终端中接口电路的发射机/接收机。在外部指定的总相位偏差测量模式中，由相位比较器预测由接收器电路和驱动器电路引起的延迟时间，即相位差。检测的相位差信号存储在相位控制电路中，相位控制电路控制从PLL电路产生的周期性定时信号。因此，作为数据缓冲器，响应于相位控制定时信号向驱动电路7施加发送数据，使从驱动电路产生的发送数据信号相对于接收到的数据信号的相位差最小。

7. 发明授权

US5062111A Error check code generating device and transmission error detecting device 失效
标题翻译：错误检查码生成装置和传输错误检测装置
公开(公告)号：US5062111A
公开(公告)日：1991-10-29
申请号：US426958
申请日：1989-10-26
申请人： Kouji Gotou , Hiroshi Kuranaga , Takeo Nakabayashi
发明人： Kouji Gotou , Hiroshi Kuranaga , Takeo Nakabayashi
IPC分类号： H03M13/00 , H03M13/09
CPC分类号： H03M13/091
摘要： There are disclosed an FCS encoder responsive to data to be transmitted for generating a frame check sequence (FCS) code to check a transmission error, and an FCS decoder for detecting an error. These FCS encoder and FCS decoder have a division circuit and a multiplication circuit each of which comprises shift registers in 16 stages and EXOR gates. Since there is no need for logical elements to be connected between the respective shift registers, this FCS encoder can be constituted to show a regular circuit layout on a semiconductor substrate.
摘要翻译：公开了一种FCS编码器，其响应于要发送的数据以产生用于检查传输错误的帧校验序列（FCS）码，以及用于检测错误的FCS解码器。这些FCS编码器和FCS解码器具有除法电路和乘法电路，每个电路包括16级移位寄存器和EXOR门。由于不需要在各个移位寄存器之间连接逻辑元件，因此可以构成该FCS编码器以在半导体基板上显示规则的电路布局。

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