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1. 发明授权

US07376016B2 Method of writing to non-volatile semiconductor memory device storing information depending on variation in level of threshold voltage 有权
标题翻译：写入根据阈值电压电平变化存储信息的非易失性半导体存储器件的方法
公开(公告)号：US07376016B2
公开(公告)日：2008-05-20
申请号：US11488621
申请日：2006-07-19
申请人： Takeshi Kajimoto , Takeshi Nakayama , Shinichi Kobayashi , Takashi Kono
发明人： Takeshi Kajimoto , Takeshi Nakayama , Shinichi Kobayashi , Takashi Kono
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/3459
摘要： In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.
摘要翻译：在闪速存储器中，在初始写入操作结束后，与经过写入的存储器单元相关联的每个位线被预充电，并且与不经过写入的存储器单元相关联的每个位线被放电并被验证以检测存储器小区阈值电压和这样检测的存储单元经受附加写入。可以验证验证，而不受流过不经过写入的存储器单元的电流的影响。所有存储单元可以准确地设置其各自的阈值电压。

2. 发明申请

US20090010070A1 Method of writing to non-volatile semiconductor memory device storing information depending on variation in level of threshold voltage 审中-公开
标题翻译：写入根据阈值电压电平变化存储信息的非易失性半导体存储器件的方法
公开(公告)号：US20090010070A1
公开(公告)日：2009-01-08
申请号：US12149422
申请日：2008-05-01
申请人： Takeshi Kajimoto , Takeshi Nakayama , Shinichi Kobayashi , Takashi Kono
发明人： Takeshi Kajimoto , Takeshi Nakayama , Shinichi Kobayashi , Takashi Kono
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/3459
摘要： In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.
摘要翻译：在闪速存储器中，在初始写入操作结束后，与经过写入的存储器单元相关联的每个位线被预充电，并且与不经过写入的存储器单元相关联的每个位线被放电并被验证以检测存储器小区阈值电压和这样检测的存储单元经受附加写入。可以验证验证，而不受流过不经过写入的存储器单元的电流的影响。所有存储单元可以准确地设置其各自的阈值电压。

3. 发明申请

US20070019478A1 Method of writing to non-volatile semiconductor memory device storing information depending on variation in level of threshold voltage 有权
标题翻译：写入根据阈值电压电平变化存储信息的非易失性半导体存储器件的方法
公开(公告)号：US20070019478A1
公开(公告)日：2007-01-25
申请号：US11488621
申请日：2006-07-19
申请人： Takeshi Kajimoto , Takeshi Nakayama , Shinichi Kobayashi , Takashi Kono
发明人： Takeshi Kajimoto , Takeshi Nakayama , Shinichi Kobayashi , Takashi Kono
IPC分类号： G11C11/34 , G11C16/06 , G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/3459
摘要： In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.
摘要翻译：在闪速存储器中，在初始写入操作结束后，与经过写入的存储器单元相关联的每个位线被预充电，并且与不经过写入的存储器单元相关联的每个位线被放电并被验证以检测存储器小区阈值电压和这样检测的存储单元经受附加写入。可以验证验证，而不受流过不经过写入的存储器单元的电流的影响。所有存储单元可以准确地设置其各自的阈值电压。

4. 发明授权

US07903460B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07903460B2
公开(公告)日：2011-03-08
申请号：US12398794
申请日：2009-03-05
申请人： Takeshi Kajimoto
发明人： Takeshi Kajimoto
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/14 , G11C16/16 , G11C2211/5641
摘要： The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states of each memory cell. In the logical erase state, a threshold voltage criterion of the memory cell is shifted to a state higher than the physical erase state. When data rewriting of the memory cell placed in the physical erase state is performed, a logical erase is performed and the threshold voltage criterion is shifted to a high voltage level. The logical erase simply shifts the voltage level of the threshold voltage criterion. Since an electrical charge accumulated in the memory cell is not moved, erasing can be done at high speed and in a short period of time.
摘要翻译：本发明提供一种能够以足够小的分割单位实现擦除/写入操作，同时将芯片面积的增加抑制到最小并且缩短擦除时间的非易失性存储器。提供两个物理擦除状态和逻辑擦除状态作为每个存储单元的阈值电压分布状态。在逻辑擦除状态下，存储单元的阈值电压准则被转移到高于物理擦除状态的状态。当执行放置在物理擦除状态的存储单元的数据重写时，执行逻辑擦除并将阈值电压标准转移到高电压电平。逻辑擦除简单地移动阈值电压准则的电压电平。由于积存在存储单元中的电荷不移动，所以可以在高速和短时间内进行擦除。

5. 发明授权

US06998879B2 Level determination circuit determining logic level of input signal 失效
标题翻译：电平确定电路确定输入信号的逻辑电平
公开(公告)号：US06998879B2
公开(公告)日：2006-02-14
申请号：US10394276
申请日：2003-03-24
申请人： Takeshi Kajimoto
发明人： Takeshi Kajimoto
IPC分类号： H03K5/22
CPC分类号： H04L25/061 , H03K5/086
摘要： An input circuit in a DRAM includes a differential amplifier circuit amplifying a potential difference between a potential of an input signal and a reference potential, an inverter outputting an inversion signal of an output signal of the differential amplifier circuit, a latch circuit holding an output signal in a preceding cycle, and two resistive elements for switching the reference potential in accordance with an output signal of the latch circuit. Thus, the reference potential is switched in accordance with the logic level of the input signal in the preceding cycle, allowing accurate determination of the logic level of the input signal.
摘要翻译： DRAM中的输入电路包括放大输入信号的电位和参考电位之间的电位差的差分放大电路，输出差分放大电路的输出信号的反相信号的反相器，保持输出信号的锁存电路在前一周期中，以及两个电阻元件，用于根据锁存电路的输出信号切换参考电位。因此，根据前一周期中的输入信号的逻辑电平来切换参考电位，从而允许准确地确定输入信号的逻辑电平。

6. 发明授权

US5446418A Ring oscillator and constant voltage generation circuit 失效
标题翻译：环形振荡器和恒压发生电路
公开(公告)号：US5446418A
公开(公告)日：1995-08-29
申请号：US147268
申请日：1993-11-05
申请人： Motoko Hara , Takeshi Kajimoto
发明人： Motoko Hara , Takeshi Kajimoto
IPC分类号： H03K3/354 , G11C11/407 , G11C11/408 , H03K3/03 , H03K3/353
CPC分类号： H03K3/0315
摘要： A ring oscillator according to the invention includes a plurality of inverters cascade-connected between an input node and an output node. Each inverter includes four transistors connected in series between a power supply node and a ground node. A first pair of transistors each have a channel sized to have an input capacitance for delaying the signal of a preceding stage inverter for a prescribed time period. A second pair of transistors are coupled to a current mirror circuit and limits current flowing through the first pair of transistors. Thus, power consumption for obtaining a signal in a prescribed cycle is reduced.
摘要翻译：根据本发明的环形振荡器包括级联连接在输入节点和输出节点之间的多个反相器。每个逆变器包括串联在电源节点和接地节点之间的四个晶体管。第一对晶体管每个具有通道，其尺寸设置成具有用于将前级反相器的信号延迟规定时间段的输入电容。第二对晶体管耦合到电流镜电路并限制流过第一对晶体管的电流。因此，减少了在规定的周期内获得信号的功耗。

7. 发明授权

US5084838A Large-scale integrated circuit device such as a wafer scale memory having improved arrangements for bypassing, redundancy, and unit integrated circuit interconnection 失效
标题翻译：大规模集成电路器件，例如具有改进的旁路，冗余和单元集成电路互连布置的晶片刻度存储器
公开(公告)号：US5084838A
公开(公告)日：1992-01-28
申请号：US391783
申请日：1989-08-09
申请人： Takeshi Kajimoto , Mitsuteru Kobayashi
发明人： Takeshi Kajimoto , Mitsuteru Kobayashi
IPC分类号： G06F11/20 , G11C8/12 , G11C29/00
CPC分类号： G11C29/006 , G11C8/12
摘要： A plurality of unit integrated circuits mounted on a large-scale integrated circuit device, for example, a wafer scale memory, are each provided with a bypass circuit which selectively shorts input and output nodes in the corresponding unit integrated circuit. By selectively bringing the bypass circuit into a transfer state, it is possible to effectively couple together all unit integrated circuits which are judged to be normal among a plurality of unit integrated circuits disposed along one row, for example. Improved redundancy arrangements are also provided, including first and second redundant elements for the unit integrated circuits, to effectively utilize the normal elements in the unit integrated circuits. Further, an improved arrangement for hierarchically connecting together the outputs of all the unit circuit blocks is provided which reduces the signal line load for the memory device.
摘要翻译：安装在大规模集成电路装置（例如，晶片刻度存储器）上的多个单元集成电路各自设置有旁路电路，其选择性地缩短相应的单元集成电路中的输入和输出节点。通过选择性地使旁路电路进入传送状态，例如可以将沿着一行布置的多个单元集成电路中被判断为正常的所有单元集成电路有效地耦合在一起。还提供了改进的冗余布置，包括用于单元集成电路的第一和第二冗余元件，以有效地利用单元集成电路中的正常元件。此外，提供了用于将所有单元电路块的输出分层连接在一起的改进布置，其减少了存储器件的信号线负载。

8. 发明授权

US5659260A Sense amplifier having a circuit for compensating for potential voltage drops caused by parasitic interconnections 失效
标题翻译：感测放大器具有用于补偿由寄生互连引起的潜在电压降的电路
公开(公告)号：US5659260A
公开(公告)日：1997-08-19
申请号：US602521
申请日：1996-02-20
申请人： Takeshi Kajimoto , Hiroshi Akamatsu
发明人： Takeshi Kajimoto , Hiroshi Akamatsu
IPC分类号： G11C11/409 , G05F1/577 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/4091 , G01R19/00
CPC分类号： G11C5/145 , G05F1/577 , G11C11/4091
摘要： A negative power supply circuit is connected via an NMOS transistor to a node receiving ground potential in a sense amplifier. A one shot pulse generation circuit provides a one shot pulse signal to the gate of the NMOS transistor. The NMOS transistor is turned on when a one shot pulse signal is applied to connect the negative power supply circuit to the node. This causes the potential of the node to be lowered to a negative potential. As a result, increase in the potential at the ground side of the sense amplifier caused by an interconnection resistance in the ground interconnection is suppressed. Therefore, variation in the potential received by the sense amplifier due to interconnection resistance can be suppressed.
摘要翻译：负电源电路通过NMOS晶体管连接到读出放大器中接收地电位的节点。单脉冲发生电路向NMOS晶体管的栅极提供单触发脉冲信号。当施加单触发脉冲信号以将负电源电路连接到节点时，NMOS晶体管导通。这导致节点的电位降低到负电位。结果，由于接地互连中的互连电阻引起的感测放大器的接地侧的电位的增加被抑制。因此，可以抑制由于互连电阻而由读出放大器接收的电位的变化。

9. 发明授权

US5600281A Oscillator circuit generating a clock signal having a temperature dependent cycle and a semiconductor memory device including the same 失效
标题翻译：产生具有温度相关周期的时钟信号的振荡器电路和包括该时钟信号的半导体存储器件
公开(公告)号：US5600281A
公开(公告)日：1997-02-04
申请号：US577354
申请日：1995-12-22
申请人： Shigeru Mori , Takeshi Kajimoto , Masanori Hayashikoshi
发明人： Shigeru Mori , Takeshi Kajimoto , Masanori Hayashikoshi
IPC分类号： G11C11/406 , G11C11/4076 , H03K3/03 , H03K3/354 , G01K7/00 , H03B5/02
CPC分类号： G11C11/4076 , G11C11/406 , H03K3/0315 , H03K3/354
摘要： In a semiconductor memory device, a constant voltage is applied to a resistor having a positive temperature coefficient, whereby a first reference current flowing through that resistor is converted into a voltage by a resistor. That voltage is converted into a second reference current by a P channel MOS transistor, whereby a second current of a value equal to the value of the second reference current flows through each of a plurality of inverters by a current mirror circuit. These inverters are connected in a ring manner to form a ring oscillator. The first reference current becomes lower as the operating temperature rises, whereby the second reference current increases. As a result, the oscillator cycle of the ring oscillator becomes shorter as the operating temperature rises.
摘要翻译：在半导体存储器件中，将恒定电压施加到具有正温度系数的电阻器，由此流过该电阻器的第一参考电流被电阻器转换成电压。该电压通过P沟道MOS晶体管转换为第二基准电流，由此通过电流镜电路使等于第二基准电流的值的第二电流流过多个反相器中的每一个。这些反相器以环形方式连接以形成环形振荡器。随着工作温度升高，第一参考电流变低，从而第二参考电流增加。结果，环路振荡器的振荡器周期随着工作温度升高而变短。

10. 发明授权

US5530397A Reference voltage generating circuit of semiconductor memory device 失效
标题翻译：半导体存储器件的基准电压发生电路
公开(公告)号：US5530397A
公开(公告)日：1996-06-25
申请号：US280971
申请日：1994-07-27
申请人： Jun Nakai , Yuto Ikeda , Takeshi Kajimoto , Yuichiro Komiya
发明人： Jun Nakai , Yuto Ikeda , Takeshi Kajimoto , Yuichiro Komiya
IPC分类号： G11C11/413 , G05F3/24 , G05F3/26 , G11C5/14 , G11C11/407 , G05F3/02
CPC分类号： G11C5/147
摘要： A reference voltage generating circuit of a DRAM includes a current mirror circuit constituted of first to fourth transistors. The gate of the third transistor is connected to the source of a fifth transistor. When a zero-power on reset signal, which becomes L on turn-on of the power supply, and becomes H after a predetermined period, is applied to the gate of the fifth transistor, and an external power supply voltage is forced to be applied to the gate of the third transistor on turn-on of the power supply, a reference voltage following the rise of the external power supply voltage is provided from the output of the current mirror circuit.
摘要翻译： DRAM的参考电压产生电路包括由第一至第四晶体管构成的电流镜电路。第三晶体管的栅极连接到第五晶体管的源极。当在第五晶体管的栅极上施加零电源复位信号，其在电源接通时变为L并且在预定周期之后变为H时，迫使外部电源电压施加在电源接通时到第三晶体管的栅极，从电流镜电路的输出提供跟随外部电源电压上升的参考电压。

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