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1. 发明申请

US20090206280A1 CHARGED-BEAM EXPOSURE APPARATUS HAVING AN IMPROVED ALIGNMENT PRECISION AND EXPOSURE METHOD 审中-公开
标题翻译：具有改进的对准精度和曝光方法的充电束曝光装置
公开(公告)号：US20090206280A1
公开(公告)日：2009-08-20
申请号：US12363123
申请日：2009-01-30
申请人： Takeshi KOSHIBA , Tetsuro NAKASUGI , Ryoichi INANAMI , Takumi OTA , Hiroyuki MIZUNO
发明人： Takeshi KOSHIBA , Tetsuro NAKASUGI , Ryoichi INANAMI , Takumi OTA , Hiroyuki MIZUNO
IPC分类号： A61N5/00 , H01J3/14
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00
摘要： The first charged-beam optical system, which is one of the charged-beam optical systems, detects first marks provided on the chips formed in the wafer. The positions of the chips made in the wafer are calculated from position data about the first marks detected. The charged-beam optical systems detect the second mark provided on a stage. The position of the beam generated by each charged-beam optical system is adjusted in accordance with position data about the second mark detected. The charged-beam optical systems are used in accordance with the positions of the chips, to thereby draw a pattern.
摘要翻译：作为带电光束光学系统之一的第一带电束光学系统检测在晶片上形成的芯片上提供的第一标记。根据关于检测到的第一标记的位置数据计算在晶片中制造的芯片的位置。带电光束光学系统检测在舞台上提供的第二标记。根据检测到的第二标记的位置数据来调整由每个带电束光学系统产生的光束的位置。根据芯片的位置使用带电束光学系统，从而绘制图案。

2. 发明申请

US20120025892A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20120025892A1
公开(公告)日：2012-02-02
申请号：US13253584
申请日：2011-10-05
申请人： Hiroyuki MIZUNO , Yusuke KANNO , Kazumasa YANAGISAWA , Yoshihiko YASU , Nobuhiro OODAIRA
发明人： Hiroyuki MIZUNO , Yusuke KANNO , Kazumasa YANAGISAWA , Yoshihiko YASU , Nobuhiro OODAIRA
IPC分类号： H03L5/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译：具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。转换电路（MIO1〜MIO4）通常用于连接电路块。

3. 发明申请

US20110208983A1 SUBSTRATE BIAS SWITCHING UNIT FOR A LOW POWER PROCESSOR 有权
标题翻译：用于低功率处理器的基板偏置开关单元
公开(公告)号：US20110208983A1
公开(公告)日：2011-08-25
申请号：US13101678
申请日：2011-05-05
申请人： Yonetaro TOTSUKA , Koichiro ISHIBASHI , Hiroyuki MIZUNO , Osamu Nishii , Kunio UCHIYAMA , Takanori SHIMURA , Asako SEKINE , Yoichi KATSUKI , Susumu NARITA
发明人： Yonetaro TOTSUKA , Koichiro ISHIBASHI , Hiroyuki MIZUNO , Osamu Nishii , Kunio UCHIYAMA , Takanori SHIMURA , Asako SEKINE , Yoichi KATSUKI , Susumu NARITA
IPC分类号： G06F1/26
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
摘要翻译：本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

4. 发明申请

US20100182076A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：US20100182076A1
公开(公告)日：2010-07-22
申请号：US12688967
申请日：2010-01-18
申请人： Hiroyuki MIZUNO , Kiyoo ITOH , Masanao YAMAOKA
发明人： Hiroyuki MIZUNO , Kiyoo ITOH , Masanao YAMAOKA
IPC分类号： G05F1/10
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit device achieving an active state in which a high speed operation is performed and an inactive state in which a low leakage state is retained while an internal logical state is retained, and a transition between the two states can be achieved at high speed with low noise and low power. A power control circuit provided between a first power-supply line for providing a first external power-supply voltage and a second power-supply line for providing a second external power-supply voltage includes an output MOSFET. A constant OFF current flows in the MOSFET even if a gate and a source of the output MOSFET are put in the same voltage, and a threshold voltage of the output MOSFET is smaller than that of an internal circuit MOSFET.
摘要翻译：实现进行高速运转的活动状态的半导体集成电路器件和保持内部逻辑状态时保持低泄漏状态的无效状态，并且可以高速地实现两种状态之间的转变噪音低，功耗低。设置在用于提供第一外部电源电压的第一电源线和用于提供第二外部电源电压的第二电源线之间的功率控制电路包括输出MOSFET。即使输出MOSFET的栅极和源极处于相同的电压，并且输出MOSFET的阈值电压小于内部电路MOSFET的阈值电压，恒定的关断电流也流入MOSFET。

5. 发明申请

US20070291564A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070291564A1
公开(公告)日：2007-12-20
申请号：US11761642
申请日：2007-06-12
申请人： Hiroyuki MIZUNO , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
发明人： Hiroyuki MIZUNO , Takeshi Sakata , Nobuhiro Oodaira , Takao Watanabe , Yusuke Kanno
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
摘要翻译：本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为过程波动很大程度。本发明提供以下典型的效果：位线BL与连接到存储单元的局部位线LBL之间的开关装置用于隔离和耦合这些位线位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BLA的最大幅度电压。读出放大器SA包括包括连接到位线BL的栅极的差分MOS对的第一电路和连接到用于全幅放大的局部位线LBL的第二电路，用于保存数据。当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

6. 发明申请

US20130035847A1 NAVIGATION SYSTEM, NAVIGATION METHOD, AND COMPUTER-READABLE STORAGE MEDIUM 审中-公开
标题翻译：导航系统，导航方法和计算机可读存储介质
公开(公告)号：US20130035847A1
公开(公告)日：2013-02-07
申请号：US13530917
申请日：2012-06-22
申请人： Junki YAMAKAWA , Hiroyuki MIZUNO
发明人： Junki YAMAKAWA , Hiroyuki MIZUNO
IPC分类号： G01C21/00
CPC分类号： G01C21/3484
摘要： Navigation systems, methods, and programs acquire evaluation information for evaluating the driving of a vehicle, evaluate the driver's driving operation for each evaluation interval having a predetermined travel distance based on the evaluation information, and display a past evaluation result and a current evaluation result at a position corresponding to each evaluation interval on a map in a mode that differs between the past evaluation result and the current evaluation result. When the vehicle arrives at an end point of the evaluation interval of the past travel from the same direction as during the past travel time, the systems, methods, and programs evaluate the driver's driving operation for a current evaluation interval along a travel track of the current travel and display the current evaluation result on the current evaluation interval at a position which corresponds to the current evaluation interval and at which the past evaluation result is displayed.
摘要翻译：导航系统，方法和程序获取用于评估车辆驾驶的评估信息，基于评估信息评估具有预定行驶距离的每个评估间隔的驾驶员的驾驶操作，并且将过去的评估结果和当前评估结果显示在在与之前的评价结果和当前的评价结果不同的模式中，对应于地图上的各评价间隔的位置。当车辆从与过去行驶时间相同的方向到达过去行驶的评估间隔的终点时，系统，方法和程序评估驾驶员对沿着行驶轨迹的当前评估间隔的驾驶操作电流行进，并且在与当前评估间隔对应的位置处显示当前评估结果，并且显示过去评估结果。

7. 发明申请

US20130018538A1 EVALUATION INDICATION SYSTEM, EVALUATION INDICATION METHOD AND COMPUTER-READABLE STORAGE MEDIUM 有权
标题翻译：评估指标体系，评估指标方法和计算机可读存储介质
公开(公告)号：US20130018538A1
公开(公告)日：2013-01-17
申请号：US13523276
申请日：2012-06-14
申请人： Naoki MIURA , Junichi NONOMURA , Junki YAMAKAWA , Hiroyuki MIZUNO
发明人： Naoki MIURA , Junichi NONOMURA , Junki YAMAKAWA , Hiroyuki MIZUNO
IPC分类号： B60W20/00 , B60W10/08 , G01C21/00 , B60W10/06
CPC分类号： G01C21/3697 , B60R16/0236 , G01C21/3469 , G01C21/3617 , Y02T10/84
摘要： Evaluation indication systems, methods, and programs are provided for a hybrid vehicle that is configured to travel in an HV mode with an internal combustion engine or in an EV mode without the internal combustion engine. The systems, methods, and programs display a current position of the hybrid vehicle on a map, acquire current evaluations of fuel consumption of the hybrid vehicle in current travel by unit sections, acquire previous evaluations of fuel consumption of the hybrid vehicle in previous travel by unit sections, and indicate current evaluation icons on the map, each of the icons being an EV icon or art HV icon. Each EV icon indicates that the hybrid vehicle has travelled within the corresponding unit section in the EV mode and each HV icon indicates that the hybrid vehicle has travelled within the corresponding unit section in the HV mode.
摘要翻译：提供了用于混合动力车辆的评估指示系统，方法和程序，所述混合动力车辆被构造成以内燃机的HV模式行驶，或者在没有内燃机的EV模式下行驶。系统，方法和程序在地图上显示混合动力车辆的当前位置，以单位部分获取当前行驶中当前对混合动力车辆的燃料消耗的评估，在先前的行程中获取混合动力车辆的燃料消耗的先前评估单位部分，并指示地图上的当前评估图标，每个图标是EV图标或艺术HV图标。每个EV图标表示混合动力车辆在EV模式中在对应的单元部分内行进，并且每个HV图标表示混合动力车辆在HV模式下的相应单元部分内行进。

8. 发明申请

US20120023313A1 PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE 有权
标题翻译：用于计算机，保存或恢复多个寄存器的处理器微架构，设备，系统，制造方法和过程
公开(公告)号：US20120023313A1
公开(公告)日：2012-01-26
申请号：US13247101
申请日：2011-09-28
申请人： Kenichi TASHIRO , Hiroyuki MIZUNO , Yuji UMEMOTO
发明人： Kenichi TASHIRO , Hiroyuki MIZUNO , Yuji UMEMOTO
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/3001 , G06F9/3004 , G06F9/30065 , G06F9/30098 , G06F9/3016
摘要： An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.
摘要翻译：电子电路（4000）包括可操作以在可编程范围内提供变化的偏置值的偏置值发生器电路（3900），以及响应于第一指令编程所述偏置值发生器的范围的指令电路（3625,4010）电路（3900），并且还响应于具有操作数的第二指令以重复地发出所述第二指令，所述操作数在作为变化的偏置值的函数确定的操作数值范围内变化。

9. 发明申请

US20130026961A1 INJECTION MOLDING MACHINE 有权
标题翻译：注塑机
公开(公告)号：US20130026961A1
公开(公告)日：2013-01-31
申请号：US13556320
申请日：2012-07-24
申请人： Noritaka OKADA , Hiroshi MORITA , Hiroyuki MIZUNO , Atsushi KATO
发明人： Noritaka OKADA , Hiroshi MORITA , Hiroyuki MIZUNO , Atsushi KATO
IPC分类号： H02P6/00
CPC分类号： H02P6/00 , B29C45/7666 , B29C2045/1792 , B29C2045/7673 , Y02P70/26 , Y02P70/261
摘要： An injection molding machine includes a motor; a driver circuit; a rectifying part; a capacitor provided between the driver circuit and the rectifying part; a bridge circuit that converts direct electric power between the driver circuit and the rectifying part into alternating electric power; a harmonics component reducing part connected to an alternating side of the bridge circuit; and a regenerative line connected to the rectifying part in parallel, wherein the bridge circuit and the harmonics component reducing part are provided in the regenerative line, and plural switching elements of the bridge circuit are turned on or off such that electric power of the motor is regenerated when a voltage of the capacitor is greater than or equal to a predetermined value, and all the switching elements are turned off when the voltage of the capacitor is less than the predetermined value.
摘要翻译：注射成型机包括马达; 驱动电路; 整改部分设置在驱动电路和整流部之间的电容器; 将驱动电路和整流部之间的直接电力转换为交流电力的桥式电路; 连接到桥接电路的交替侧的谐波分量减少部分; 以及并联连接到整流部的再生线，其中，所述桥接电路和所述谐波成分减少部设置在所述再生线路中，所述桥接电路的多个开关元件导通或截止，使得所述电动机的电力为当电容器的电压大于或等于预定值时再生，并且当电容器的电压小于预定值时，所有开关元件都截止。

10. 发明申请

US20130026956A1 INJECTION MOLDING MACHINE 有权
标题翻译：注塑机
公开(公告)号：US20130026956A1
公开(公告)日：2013-01-31
申请号：US13556305
申请日：2012-07-24
申请人： Atsushi KATO , Hiroshi MORITA , Hiroyuki MIZUNO , Noritaka OKADA
发明人： Atsushi KATO , Hiroshi MORITA , Hiroyuki MIZUNO , Noritaka OKADA
IPC分类号： H02P3/14
CPC分类号： H02P6/00 , B29C45/7666 , B29C2045/1792 , B29C2045/7673 , Y02P70/26 , Y02P70/261
摘要： An injection molding machine according to the invention includes a motor, a driver circuit that drives the motor; and a rectifying part that supplies electric power to the driver circuit. A regenerative line for regenerative electric power of the motor is connected to the rectifying part in parallel. A converting part and a harmonics component reducing part are provided in the regenerative line. The converting part converts direct electric power between the driver circuit and the rectifying part into alternating electric power which is input to the harmonics component reducing part.
摘要翻译：根据本发明的注射成型机包括马达，驱动马达的驱动电路; 以及向驱动电路供给电力的整流部。马达的再生电力再生线并联连接到整流部。在再生线路中设置A转换部和谐波成分减少部。转换部分将驱动电路和整流部分之间的直接电力转换为输入到谐波分量减少部分的交流电力。

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