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    • 2. 发明授权
    • Bit synchronizing circuit having high synchronization characteristics
    • 位同步电路具有高同步特性
    • US6111926A
    • 2000-08-29
    • US999071
    • 1997-12-29
    • Takeshi ImamuraSatoshi Sato
    • Takeshi ImamuraSatoshi Sato
    • H03L7/099H04L7/033H04L7/04
    • H03L7/0992H04L7/0331
    • A bit synchronizing circuit is arranged by a bit synchronization counter constructed of an up/down counter or an adding/subtracting counter; an edge detector for detecting an edge of an input NRZ signal to output an edge detection pulse; two sets of edge number counters for counting total numbers of edge detection pulses outputted from the edge detector during a 1 cycle of the counting operation by the bit synchronization counter; and two sets of registers for fetching the count value of the bit synchronization counter at the time instant every time the edge detector outputs the edge detection pulse, and also for storing an accumulation value of the count values fetched during the 1 cycle of the counting operation by the bit synchronization counter. Both the two edge number counters and the two registers are operated with shifts of a half cycle, respectively. This bit synchronization circuit is further arranged by a judging circuit for judging a synchronization shift amount between the input NRZ signal and the counting operation by the bit synchronization counter based on the count values of the two edge number counters and the accumulate values stored in the two registers, and for outputting a correction signal corresponding to the judgment result to the bit synchronization counter.
    • 位同步电路由由上/下计数器或加减计数器构成的位同步计数器来布置; 用于检测输入NRZ信号的边沿以输出边缘检测脉冲的边缘检测器; 两组边缘数计数器,用于在由比特同步计数器进行的计数操作的1个周期期间计数从边缘检测器输出的边缘检测脉冲的总数; 以及两组寄存器,用于在每次边沿检测器输出边缘检测脉冲时在时刻获取位同步计数器的计数值,并且还用于存储在计数操作的1个周期期间取出的计数值的累加值 由位同步计数器。 两个边缘数字计数器和两个寄存器分别以半个周期的移位操作。 该比特同步电路还由一个判断电路进行布置,该判断电路基于两个边缘号码计数器的计数值和存储在两个边缘号码计数器中的累加值来判断输入NRZ信号与位同步计数器的计数操作之间的同步移位量 寄存器,并将与判断结果相对应的校正信号输出到位同步计数器。