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1. 发明授权

US6036346A Semiconductor manufacturing process simulation apparatus for calculating a pressure field generated by a dislocation loop 失效
标题翻译：用于计算由位错环产生的压力场的半导体制造工艺模拟装置
公开(公告)号：US6036346A
公开(公告)日：2000-03-14
申请号：US859265
申请日：1997-05-20
申请人： Takeshi Hino , Toshihiro Hyodo
发明人： Takeshi Hino , Toshihiro Hyodo
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5018
摘要： A semiconductor manufacturing process simulation apparatus using a diffusion model in which a dislocation loop generated in a crystalline substrate during an ion implantation process of a semiconductor manufacturing process is considered with respect to a diffusion in a heat treatment process subsequent to the ion implantation process. An ion implantation process simulating part simulates an ion implantation process. A model generating part generates a diffusion model in which contribution of dislocation loops is considered, the dislocation loops being formed in the substrate during the ion implantation process. A heat treatment process simulating part simulates a heat treatment process subsequent to the ion implantation process, the diffusion model generated by the model generating part being used for simulating diffusion of impurities in the substrate during the heat treatment process. A pressure field generated by the dislocation loops in the substrate is defined in the diffusion model by a function of a distance from a layer in which the dislocation loops are formed.
摘要翻译：考虑到在离子注入工艺之后的热处理工艺中的扩散，考虑了在半导体制造工艺的离子注入工艺期间在晶体衬底中产生的位错环的扩散模型的半导体制造工艺模拟装置。离子注入工艺模拟部分模拟离子注入工艺。模型生成部分产生扩散模型，其中考虑位错环的贡献，在离子注入过程期间在衬底中形成位错环。模拟部件的热处理工艺模拟离子注入工艺之后的热处理工艺，由模型产生部分生成的扩散模型用于在热处理过程中模拟衬底中杂质的扩散。在扩散模型中通过与形成位错环的层的距离的函数来限定由基板中的位错环产生的压力场。

2. 发明授权

US5426321A Semiconductor memory element and semiconductor memory device 失效
标题翻译：半导体存储元件和半导体存储器件
公开(公告)号：US5426321A
公开(公告)日：1995-06-20
申请号：US978808
申请日：1992-11-19
申请人： Toshihiro Hyodo
发明人： Toshihiro Hyodo
IPC分类号： H01L21/8246 , H01L27/112 , H01L29/78
CPC分类号： H01L29/7827 , H01L27/112
摘要： The present invention relates to a semiconductor memory device having a planner cell structure. A source with a large area is formed on a P-type silicon substrate, a plurality of strip-like word lines are formed in parallel to each other on the source, gate oxide films are formed on both side walls of each of the word lines, and an epitaxial layer is formed between the word lines. A plurality of strip-like bit lines are formed in parallel to each other perpendicularly to the word lines on the oxide film, and the epitaxial layer, and a drain is formed in the epitaxial layer under a polycrystalline silicon film of the bit line. A channel is formed in contact with the gate oxide film between the drain and the source in the epitaxial layer, and an electric current flows in a longitudinal direction when a memory element becomes ON.
摘要翻译：本发明涉及一种具有计划单元结构的半导体存储器件。在P型硅衬底上形成具有大面积的源极，在源极上彼此平行地形成多个条状字线，在每个字线的两个侧壁上形成栅极氧化膜并且在字线之间形成外延层。多个条状位线垂直于氧化膜上的字线彼此平行地形成，并且外延层和在位线的多晶硅膜下的外延层中形成漏极。在外延层中的漏极和源极之间形成与栅极氧化膜接触的沟道，并且当存储元件导通时，电流沿纵向流动。

3. 发明授权

US5787269A Process simulation apparatus and method for selecting an optimum simulation model for a semiconductor manufacturing process 失效
标题翻译：用于选择半导体制造工艺的最佳模拟模型的工艺模拟装置和方法
公开(公告)号：US5787269A
公开(公告)日：1998-07-28
申请号：US531231
申请日：1995-09-19
申请人： Toshihiro Hyodo
发明人： Toshihiro Hyodo
IPC分类号： H01L21/02 , G06F11/26 , G06F17/50 , G06F19/00 , G06Q50/00 , G06Q50/04 , H01L21/00 , G06F11/30
CPC分类号： G06F11/261 , G06F17/5018
摘要： A process simulation apparatus simulates a manufacturing process of a semiconductor device which manufacturing process comprising various processes including an ion implantation process and a diffusion process. Process sequence data which represents conditions of a two-dimensional simulation for each process is input to a memory unit. The memory unit stores the process sequence data and also stores condition information for various simulation models usable for each process. An optimum simulation model for each process is selected for performing a two-dimensional simulation for each process. The semiconductor device manufacturing process is simulated by a two-dimensional simulation method using the selected optimum simulation model.
摘要翻译：工艺模拟装置模拟包括离子注入工艺和扩散工艺的各种工艺的制造工艺的半导体器件的制造工艺。将表示每个处理的二维模拟的条件的处理序列数据输入到存储器单元。存储单元存储处理序列数据，并且还存储可用于每个处理的各种模拟模型的条件信息。选择每个过程的最佳模拟模型，以对每个过程执行二维模拟。半导体器件制造工艺通过使用所选择的最优模拟模型的二维模拟方法进行模拟。

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