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    • 6. 发明授权
    • Semiconductor manufacturing process simulation apparatus for calculating
a pressure field generated by a dislocation loop
    • 用于计算由位错环产生的压力场的半导体制造工艺模拟装置
    • US6036346A
    • 2000-03-14
    • US859265
    • 1997-05-20
    • Takeshi HinoToshihiro Hyodo
    • Takeshi HinoToshihiro Hyodo
    • G06F17/50G06F19/00
    • G06F17/5018
    • A semiconductor manufacturing process simulation apparatus using a diffusion model in which a dislocation loop generated in a crystalline substrate during an ion implantation process of a semiconductor manufacturing process is considered with respect to a diffusion in a heat treatment process subsequent to the ion implantation process. An ion implantation process simulating part simulates an ion implantation process. A model generating part generates a diffusion model in which contribution of dislocation loops is considered, the dislocation loops being formed in the substrate during the ion implantation process. A heat treatment process simulating part simulates a heat treatment process subsequent to the ion implantation process, the diffusion model generated by the model generating part being used for simulating diffusion of impurities in the substrate during the heat treatment process. A pressure field generated by the dislocation loops in the substrate is defined in the diffusion model by a function of a distance from a layer in which the dislocation loops are formed.
    • 考虑到在离子注入工艺之后的热处理工艺中的扩散,考虑了在半导体制造工艺的离子注入工艺期间在晶体衬底中产生的位错环的扩散模型的半导体制造工艺模拟装置。 离子注入工艺模拟部分模拟离子注入工艺。 模型生成部分产生扩散模型,其中考虑位错环的贡献,在离子注入过程期间在衬底中形成位错环。 模拟部件的热处理工艺模拟离子注入工艺之后的热处理工艺,由模型产生部分生成的扩散模型用于在热处理过程中模拟衬底中杂质的扩散。 在扩散模型中通过与形成位错环的层的距离的函数来限定由基板中的位错环产生的压力场。