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1. 发明授权

US07132850B2 Semiconductor integrated circuit and circuit design apparatus 失效
标题翻译：半导体集成电路和电路设计装置
公开(公告)号：US07132850B2
公开(公告)日：2006-11-07
申请号：US10689708
申请日：2003-10-22
申请人： Takeshi Hashizume , Takenobu Iwao
发明人： Takeshi Hashizume , Takenobu Iwao
IPC分类号： H03K19/177
CPC分类号： G06F17/5045
摘要： A semiconductor integrated circuit includes a memory for holding data of a logic circuit inputs or outputs. The memory is composed of logic cells, and is placed in a logic region. Thus, the semiconductor integrated circuit can prevent forming wasted space, in which no circuit component is built, and reduce its area and power consumption. It can reduce the design period of the memory as compared with the case where hard macro cells are used.
摘要翻译：半导体集成电路包括用于保存逻辑电路输入或输出的数据的存储器。存储器由逻辑单元组成，并被放置在逻辑区域中。因此，半导体集成电路可以防止形成浪费的空间，其中不构成电路部件，并且减小其面积和功耗。与使用硬宏单元的情况相比，可以减少存储器的设计周期。

2. 发明授权

US5945846A Clock driver circuit in a centrally located macro cell layout region 失效
标题翻译：时钟驱动电路位于中央位置的宏单元布局区域
公开(公告)号：US5945846A
公开(公告)日：1999-08-31
申请号：US867391
申请日：1997-06-02
申请人： Takenobu Iwao , Nobuyuki Ikeda , Miho Yokota
发明人： Takenobu Iwao , Nobuyuki Ikeda , Miho Yokota
IPC分类号： H01L21/822 , G11C11/4193 , H01L21/82 , H01L27/02 , H01L27/04 , H01L27/118 , H03K19/01 , H01L27/10
CPC分类号： H01L27/0207 , H01L27/11803
摘要： A clock driver circuit is furnished in a centrally located macro cell layout region. The clock driver circuit has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a first and a second common line, and the input and output nodes of the main drivers are short-circuited by the second and a third common line. A plurality of clock driver circuits are formed predetermined distances apart and arranged to intersect the clock driver circuit perpendicularly. Each of the clock driver circuits has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a fourth and a fifth common line, and the input and output nodes of the main drivers are short-circuited by the fifth and a sixth common line. The third and the fourth common lines are interconnected. The sixth common line is connected to clock signal supply lines which in turn are connected to a plurality of second macro cells.
摘要翻译：时钟驱动器电路位于中央位置的宏单元布局区域。时钟驱动器电路具有多个预驱动器和多个主驱动器。预驱动器的输入和输出节点由第一和第二公共线短路，并且主驱动器的输入和输出节点由第二和第三公共线短路。多个时钟驱动器电路形成为预定的距离，并被布置为垂直地与时钟驱动器电路相交。每个时钟驱动电路具有多个预驱动器和多个主驱动器。预驱动器的输入和输出节点由第四和第五公共线短路，主驱动器的输入和输出节点由第五和第六公共线短路。第三条和第四条公用线相互连接。第六公共线与连接到多个第二宏小区的时钟信号供给线连接。

3. 发明授权

US5969544A Clock driver circuit and semiconductor integrated circuit device incorporating the clock driver circuit 失效
标题翻译：时钟驱动电路和集成了时钟驱动电路的半导体集成电路器件
公开(公告)号：US5969544A
公开(公告)日：1999-10-19
申请号：US867851
申请日：1997-06-03
申请人： Takenobu Iwao , Nobuyuki Ikeda , Miho Yokota
发明人： Takenobu Iwao , Nobuyuki Ikeda , Miho Yokota
IPC分类号： H01L21/82 , H01L27/118 , H03K19/0175 , H03K19/00 , H01L25/00
CPC分类号： H01L27/11807
摘要： A plurality of macro cell layout regions 9 in cell regions 2 on a semiconductor substrate 1 are divided into three portions in a second direction. Each of the divided portions is provided with basic circuits 14a through 14c. In each basic circuit, a first common line 16 is connected to an output node of a clock input driver 11 via a clock output line 17. A plurality of predrivers 15(1) through 15(n) have their input nodes IN connected to the first common line 16 and have their output nodes OUT connected to a second common line 18. A plurality of main drivers 19(1) through 19mhave their input nodes IN connected to the second common line 18 and have their output nodes OUT connected to a third common line 20. The third common line is connected to a plurality of clock signal supply lines 21(1) through 21(s) commonly provided to the basic circuits 14a through 14c. The clock signal supply lines 21(1) through 21(s) are connected to clock input nodes of internal circuits 22 each requiring a clock signal.
摘要翻译：半导体衬底1上的单元区域2中的多个宏单元布局区域9在第二方向上分成三部分。每个分割部分设置有基本电路14a至14c。在每个基本电路中，第一公共线16经由时钟输出线17连接到时钟输入驱动器11的输出节点。多个预驱动器15（1）至15（n）的输入节点IN连接到第一公共线16并且其输出节点OUT连接到第二公共线18.多个主驱动器19（1）至19m使其输入节点IN连接到第二公共线18并且使其输出节点OUT连接到第三公共线18。公共线20.第三公共线连接到通常提供给基本电路14a至14c的多个时钟信号提供线21（1）至21（s）。时钟信号提供线21（1）至21（s）连接到每个需要时钟信号的内部电路22的时钟输入节点。

4. 发明授权

US06355948B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06355948B2
公开(公告)日：2002-03-12
申请号：US09413750
申请日：1999-10-06
申请人： Takenobu Iwao , Ryuichi Sakano
发明人： Takenobu Iwao , Ryuichi Sakano
IPC分类号： H01L2710
CPC分类号： H01L27/11807
摘要： There is provided a semiconductor integrated circuit device having a macro cell structure including: a rectangular macro cell region formed on a semiconductor substrate; a first diffusion region having the minimum permissible width, formed apart at least by a minimum inter-diffusion distance from both left and right side ends in upper and lower sides of the macro cell region, and formed in the vicinity of both upper and lower ends of the macro cell region; and a second diffusion region in which a well contact is formed. The first diffusion region is electrically connected with the second diffusion region.
摘要翻译：提供一种具有宏观单元结构的半导体集成电路器件，包括：形成在半导体衬底上的矩形宏单元区域; 具有最小允许宽度的第一扩散区域至少形成在宏小区区域的上侧和下侧中的左右侧端部之间的最小相互扩散距离，并且形成在上端和下端附近的宏小区域; 以及形成有阱接触的第二扩散区域。第一扩散区与第二扩散区电连接。

5. 发明授权

US06734547B2 Semiconductor wiring structure having divided power lines and ground lines on the same layer 失效
标题翻译：半导体配线结构在同一层上具有划分的电源线和接地线
公开(公告)号：US06734547B2
公开(公告)日：2004-05-11
申请号：US10212063
申请日：2002-08-06
申请人： Takenobu Iwao
发明人： Takenobu Iwao
IPC分类号： H01L2348
CPC分类号： H01L27/0203 , H01L23/5286 , H01L27/118 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device comprises vertical power supply wiring 12 divided into first and second narrow-width vertical power supply wirings 12a and 12b, vertical ground wiring 14 disposed in parallel with vertical power supply wiring 12 and divided into first and second narrow-width vertical ground wirings 14a and 14b, auxiliary vertical power supply wiring 22 connecting first narrow-width vertical power supply wiring 12a and second narrow-width vertical power supply wiring 12b, and auxiliary vertical ground wiring 24 connecting first narrow-width vertical ground wiring 14a and second narrow-width vertical ground wiring 14b.
摘要翻译：半导体集成电路器件包括分为第一和第二窄宽垂直电源布线12a和12b的垂直电源布线12，与垂直电源布线12并联设置的垂直接地布线14，并分成第一和第二窄宽垂直线接地布线14a和14b，连接第一窄宽垂直电源布线12a和第二窄宽垂直电源布线12b的辅助垂直电源布线22和连接第一窄宽垂直接地布线14a和第二窄宽垂直布线窄宽度的接地布线14b。

6. 发明授权

US6091088A Macro cell 失效
标题翻译：宏单元格
公开(公告)号：US6091088A
公开(公告)日：2000-07-18
申请号：US15068
申请日：1998-01-28
申请人： Yoshiaki Arima , Takenobu Iwao , Nobuyuki Ikeda , Shuichi Kato
发明人： Yoshiaki Arima , Takenobu Iwao , Nobuyuki Ikeda , Shuichi Kato
IPC分类号： H01L21/82 , H01L27/118 , H01L27/10
CPC分类号： H01L27/11807
摘要： A macro cell of field effect transistors includes source-drain areas respectively divided into a contact area and a non-contact area. One source-drain area of two of the source-drain areas located on opposite sides of the effective width portion of a gate electrode has a contact area at an upper portion and a non-contact area at a lower portion while the other source-drain area has the non-contact area at its upper portion and the contact area at its lower portion. The distance between effective width portions of gate electrodes where the non-contact area is located is smaller than the distance between effective width portions of gate electrodes where the contact area is located.
摘要翻译：场效应晶体管的宏单元包括分别被分成接触区域和非接触区域的源极 - 漏极区域。位于栅电极的有效宽度部分相对侧的源极 - 漏极区域中的两个源极 - 漏极区域在上部具有接触区域，而在下部部分处具有非接触区域，而另一个源极 - 漏极区域在其上部具有非接触区域，在其下部具有接触区域。非接触区域所在的栅电极的有效宽度部分之间的距离小于接触区域所在的栅电极的有效宽度部分之间的距离。

7. 发明授权

US5994726A Field effect transistor array including refractory metal silicide interconnection layer 失效
$Field effect transistor array including refractory metal silicide interconnection layer$
标题翻译：场效应晶体管阵列包括难熔金属硅化物互连层
公开(公告)号：US5994726A
公开(公告)日：1999-11-30
申请号：US961142
申请日：1997-10-30
申请人： Nobuyuki Ikeda , Takenobu Iwao , Miho Yokota , Shuichi Kato
发明人： Nobuyuki Ikeda , Takenobu Iwao , Miho Yokota , Shuichi Kato
IPC分类号： H01L21/28 , H01L21/82 , H01L27/118
CPC分类号： H01L27/118
摘要： Connection between a PMOS transistor and an NMOS transistor is made through a refractory metal salicide layer in the source and drain regions of these transistors. The salicide is low in resistance, thereby partially substituting for a first Al wiring in intracell wiring. The resulting empty area provides a wiring area and, hence, the freedom of chip layout is enhanced. Besides, in a microcell which constitutes a logic circuit, such as a gate array, lateral wiring grid dots can be utilized as a wiring area.
摘要翻译： PMOS晶体管和NMOS晶体管之间的连接通过这些晶体管的源极和漏极区域中的难熔金属硅化物层制成。自杀剂的电阻很低，从而部分地代替了细胞内线路中的第一个Al布线。所产生的空白区域提供布线区域，因此提高了芯片布局的自由度。此外，在构成诸如门阵列的逻辑电路的微单元中，可以将横向布线网格点用作布线区域。

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