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1. 发明授权

US06715117B2 Method of testing a semiconductor memory device 有权
标题翻译：测试半导体存储器件的方法
公开(公告)号：US06715117B2
公开(公告)日：2004-03-30
申请号：US09761847
申请日：2001-01-18
申请人： Atsuo Mangyo , Manabu Miura , Makoto Hatakenaka
发明人： Atsuo Mangyo , Manabu Miura , Makoto Hatakenaka
IPC分类号： G11C2900
CPC分类号： G11C29/48 , G11C29/08
摘要： A method for testing a semiconductor memory device according to one embodiment comprises the steps of: checking data in all addresses of the semiconductor memory device for correctness in-units of m×n bits: ending if it is determined that data in all the semiconductor memory device; if there is a defective address, comparing each m-bit data constituting the (m×n)-bit data corresponding to the defective address with its expected value; and if the comparison result indicates that the m-bit data is erroneous, determining whether the defective semiconductor memory device can be repaired. Due to this step, man hours required for testing a semiconductor memory device having a wide data bus of an (m×n)-bit width can be considerably reduced.
摘要翻译：根据一个实施例的用于测试半导体存储器件的方法包括以下步骤：检查半导体存储器件的所有地址中的数据，以确定m×n位的单位的正确性：如果确定所有半导体存储器件中的数据，则结束; 如果存在缺陷地址，则将构成与缺陷地址相对应的（m×n）位数据的每个m位数据与其期望值进行比较; 并且如果比较结果表明m位数据是错误的，则确定是否可以修复有缺陷的半导体存储器件。由于该步骤，可以显着地减少测试具有宽（mxn）位宽的数据总线的半导体存储器件所需的工时。

2. 发明授权

US07237175B2 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US07237175B2
公开(公告)日：2007-06-26
申请号：US10193319
申请日：2002-07-12
申请人： Makoto Hatakenaka , Koji Nii , Atsuo Mangyo , Takeshi Fujino
发明人： Makoto Hatakenaka , Koji Nii , Atsuo Mangyo , Takeshi Fujino
IPC分类号： G11C29/00
CPC分类号： G06F11/1012
摘要： When to a memory cell array 21 a read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into memory units 31 to 37 each of which has four bits which are arranged along a direction of a word line. On writing the 7-bit data in the memory cell array, bits of the 7-bit data that are different from one another are written as written bit data along the direction of the word line in the memory units 31 to 37, respectively. In the 7-bit data, the written bit data has an interval of four bits. Error correcting circuits performs an error correction of the 7-bit data in each of the 7-bit data.
摘要翻译：对于存储单元阵列21，对其中将3位的奇偶校验位加到4位的数据的7位数据执行读/写操作，关于7位的每一位执行错误校正数据。存储单元阵列被分成存储器单元31至37，每个存储单元具有沿着字线的方向布置的四位。在将7位数据写入存储单元阵列时，7位数据彼此不同的位被分别写入存储单元31至37中的字线方向的写入位数据。在7位数据中，写入位数据的间隔为4位。误差校正电路对7位数据中的每一个执行7位数据的纠错。

3. 发明授权

US06724237B2 Semiconductor integrated circuit for multi-chip package with means to optimize internal drive capacity 有权
标题翻译：用于多芯片封装的半导体集成电路，具有优化内部驱动能力的手段
公开(公告)号：US06724237B2
公开(公告)日：2004-04-20
申请号：US10212842
申请日：2002-08-07
申请人： Takekazu Yamashita , Makoto Hatakenaka , Manabu Miura
发明人： Takekazu Yamashita , Makoto Hatakenaka , Manabu Miura
IPC分类号： G01R3127
CPC分类号： H03K19/017581 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H03K17/164 , Y10T307/50 , H01L2924/00014
摘要： A semiconductor integrated circuit can variably set the driving power of all or part of internal input/output terminals and internal output terminals used within a multi-chip package. It can increase the driving power at an individual wafer test before packaging to sufficiently drive a load connected between a tester and the internal input/output terminals and internal output terminals, and can reduce the driving power after packaging. It can prevent noise and power consumption from being increased.
摘要翻译：半导体集成电路可以可变地设置在多芯片封装内使用的内部输入/输出端子和内部输出端子的全部或部分的驱动功率。在包装之前，可以在单个晶片测试时增加驱动功率，以充分驱动连接在测试器与内部输入/输出端子和内部输出端子之间的负载，并且可以降低封装后的驱动功率。可以防止噪音和功耗的增加。

4. 发明授权

US06512707B2 Semiconductor integrated circuit device allowing accurate evaluation of access time of memory core contained therein and access time evaluating method 有权
公开(公告)号：US06512707B2
公开(公告)日：2003-01-28
申请号：US09837164
申请日：2001-04-19
申请人： Manabu Miura , Makoto Hatakenaka
发明人： Manabu Miura , Makoto Hatakenaka
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C11/401 , G11C29/50 , G11C29/50012
摘要： An external clock signal is transmitted as a clock signal to a memory core through a first signal transmitting path. In response to activation of the clock signal CLK, memory core starts a read operation. Read data output from memory core is latched by a latch circuit. An external signal designating a latch timing is transmitted as a latch timing signal to the latch circuit through a second signal transmitting path. A delay circuit is provided in at least one of the first and second signal transmitting paths, so that the first and second signal transmitting paths come to have the same signal delay.

5. 发明授权

US5949268A Variable delay circuit for varying delay time and pulse width 失效
标题翻译：可变延迟电路，用于改变延迟时间和脉冲宽度
公开(公告)号：US5949268A
公开(公告)日：1999-09-07
申请号：US914803
申请日：1997-08-15
申请人： Manabu Miura , Makoto Hatakenaka
发明人： Manabu Miura , Makoto Hatakenaka
IPC分类号： H03K5/04 , H03K5/13 , H03K17/16 , H03K17/687
CPC分类号： H03K17/164 , H03K5/131
摘要： A variable delay circuit for controlling delay time includes P channel transistors connected in parallel, with respective source electrodes connected to a power supply, respective drain electrodes connected to an output terminal for providing delayed signal, and respective gate electrodes connected to respective control signal input terminals for receiving control signals. The circuit further includes N channel transistors with respective source electrodes connected to ground, respective drain electrodes connected to the output terminal, and respective gate electrode connected to the respective control signal input terminals. Identical or mutually inverted data signals or control signals are supplied to the respective gate electrodes of the P channel transistors and the respective gate electrodes of the N channel transistors.
摘要翻译：用于控制延迟时间的可变延迟电路包括并联连接的P沟道晶体管，各个源电极连接到电源，连接到用于提供延迟信号的输出端的相应漏电极以及连接到相应控制信号输入端的各个栅电极用于接收控制信号。电路还包括具有连接到地的各个源极的N沟道晶体管，连接到输出端的相应的漏极和连接到各个控制信号输入端的相应的栅电极。将相同或相互反转的数据信号或控制信号提供给P沟道晶体管的各个栅电极和N沟道晶体管的各个栅电极。

6. 发明授权

US06756803B2 Semiconductor device downsizing its built-in driver 失效
标题翻译：半导体器件缩小其内置驱动器
公开(公告)号：US06756803B2
公开(公告)日：2004-06-29
申请号：US10330072
申请日：2002-12-30
申请人： Manabu Miura , Makoto Hatakenaka , Takekazu Yamashita
发明人： Manabu Miura , Makoto Hatakenaka , Takekazu Yamashita
IPC分类号： G01R3102
CPC分类号： G01R31/2884 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/49175 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device includes a first pad, a second pad, a first buffer and a second buffer. The first pad is connected to another semiconductor device in a multi-chip package, and the second pad makes a probing connection in a wafer test. The first buffer drives the another semiconductor device connected to the first pad. The second buffer, being driven by the first buffer, drives a load capacitance of a tester connected to the second pad with the driving power greater than the driving power of the first buffer, and has its active/inactive state controlled by a control signal. The semiconductor device can provide the driving power necessary for the wafer test, and drive the another semiconductor device with preventing generation of drive noise and suppressing current consumption in the normal operation of the multi-chip package.
摘要翻译：半导体器件包括第一焊盘，第二焊盘，第一缓冲器和第二缓冲器。第一焊盘以多芯片封装连接到另一半导体器件，并且第二焊盘在晶片测试中进行探测连接。第一缓冲器驱动连接到第一焊盘的另一个半导体器件。由第一缓冲器驱动的第二缓冲器以大于第一缓冲器的驱动功率的驱动功率驱动连接到第二焊盘的测试仪的负载电容，并且由控制信号控制其主动/不活动状态。半导体器件可以提供晶片测试所需的驱动功率，并驱动另一半导体器件，防止产生驱动噪声并抑制多芯片封装的正常工作中的电流消耗。

7. 发明授权

US06570572B1 Line delay generator using one-port RAM 有权
标题翻译：线路延迟发生器使用单端口RAM
公开(公告)号：US06570572B1
公开(公告)日：2003-05-27
申请号：US09303623
申请日：1999-05-03
申请人： Manabu Miura , Makoto Hatakenaka , Mikio Tada
发明人： Manabu Miura , Makoto Hatakenaka , Mikio Tada
IPC分类号： G09G539
CPC分类号： G06F5/10 , H04N5/14
摘要： A line delay generator including a packetizing circuit, one port RAM and a RAM controller. The RAM controller provides the one port RAM with a write command to write packet data generated by the packetizing circuit, and with a read command to read any one or more packet data currently stored in the one port RAM, and output them as line delay data. The line delay generator can solve a problem involved in a conventional line delay generator in that because m (positive integer) two-port FIFOs must be connected in cascade to generate m line delay data, the FIFO memory becomes bulky.
摘要翻译：线延迟发生器，包括分组化电路，一个端口RAM和一个RAM控制器。 RAM控制器为单端口RAM提供写入命令，以写入由分组化电路产生的分组数据，并且读取命令读取当前存储在一个端口RAM中的任何一个或多个分组数据，并将其作为行延迟数据输出。线路延迟发生器可以解决传统线路延迟发生器中涉及的问题，因为m（正整数）双端口FIFO必须级联连接以产生m线延迟数据，因此FIFO存储器变得庞大。

8. 发明授权

US6092227A Test circuit 失效
标题翻译：测试电路
公开(公告)号：US6092227A
公开(公告)日：2000-07-18
申请号：US18934
申请日：1998-02-05
申请人： Hideki Toki , Akira Kitaguchi , Makoto Hatakenaka , Kiyoyuki Shiroshima , Masaaki Matsuo , Tsuyoshi Saitoh
发明人： Hideki Toki , Akira Kitaguchi , Makoto Hatakenaka , Kiyoyuki Shiroshima , Masaaki Matsuo , Tsuyoshi Saitoh
IPC分类号： G01R31/28 , G06F11/22 , G11C11/413 , G11C29/10 , G11C29/34 , G11C29/36 , G11C29/38 , G11C29/56
CPC分类号： G11C29/34 , G11C29/36 , G11C29/38 , G11C29/10
摘要： A test circuit includes a writing unit that outputs m-bit data captured upon receipt of a clock signal, branches the m-bit data n identical m-bit data signals, and stores the n m-bit data signals in a memory device. A function determining unit reads the n m-bit data signals from the memory, compares one of the n m-bit data signals to an m-bit expected value, and determines coincidence or non-coincidence between the n m-bit data signal and an expected value.
摘要翻译：测试电路包括写入单元，其输出接收到时钟信号时捕获的m位数据，分配m位数据n个相同的m位数据信号，并将n个m位数据信号存储在存储器件中。功能确定单元从存储器读取n个m位数据信号，将n个m位数据信号中的一个与m位预期值进行比较，并且确定n个m位数据信号和一个预期的价值。

9. 发明授权

US5910181A Semiconductor integrated circuit device comprising synchronous DRAM core and logic circuit integrated into a single chip and method of testing the synchronous DRAM core 失效
标题翻译：半导体集成电路器件包括同步DRAM核心和逻辑电路集成到单个芯片中以及测试同步DRAM内核的方法
公开(公告)号：US5910181A
公开(公告)日：1999-06-08
申请号：US964236
申请日：1997-11-04
申请人： Makoto Hatakenaka , Akira Yamazaki , Shigeki Tomishima , Tadato Yamagata
发明人： Makoto Hatakenaka , Akira Yamazaki , Shigeki Tomishima , Tadato Yamagata
IPC分类号： G11C11/407 , G11C11/401 , G11C29/02 , G11C29/14 , G11C29/16 , G11C29/48 , G06F11/00
CPC分类号： G11C29/16 , G11C29/48
摘要： A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector, and are provided to the core unit of the synchronous dynamic random access memory for testing.
摘要翻译：半导体集成电路器件包括集成在单个半导体芯片上的逻辑电路和包括核心单元的同步动态随机存取存储器。半导体集成电路装置包括：同步动态随机存取存储器控制电路，其从逻辑电路接收用于同步动态随机存取存储器的外部控制信号，并将内部控制信号输出到同步动态随机存取存储器的核心单元。对于半导体集成电路器件的测试，通过外部端子提供外部测试信号。外部测试信号由选择器选择，并提供给同步动态随机存取存储器的核心单元进行测试。

10. 发明授权

US5491438A Synchronized clock generating apparatus 失效
标题翻译：同步时钟发生装置
公开(公告)号：US5491438A
公开(公告)日：1996-02-13
申请号：US289837
申请日：1994-08-12
申请人： Yukio Miyazaki , Takenori Okitaka , Makoto Hatakenaka , Junji Mano
发明人： Yukio Miyazaki , Takenori Okitaka , Makoto Hatakenaka , Junji Mano
IPC分类号： G06F1/10 , H03K5/00 , H03K5/13 , H04L7/033 , H03L7/00
CPC分类号： H04L7/0338 , G06F1/10 , H03K5/133 , H03K2005/00234
摘要： A synchronized clock generating apparatus includes a delayed clock generating circuit including a plurality of serially connected delaying elements for generating delayed clock signals delayed successively relative to an incoming basic clock signal. Storage means includes a plurality of storage elements storing therein a predetermined level in response to transitions occurring in associated ones of said basic and delayed clock signals after a trigger signal which is asynchronous with the basic clock signal is applied thereto. A clock selection logic circuit is controlled by the output signal of the storage means for detecting the clock signal transition occurring closest in time to the application of the asynchronous trigger signal, and for selecting a desired one of said clock signals, based on the result of the detection, as a synchronized clock signal output.
摘要翻译：同步时钟发生装置包括延迟时钟产生电路，其包括多个串行连接的延迟元件，用于产生相对于输入的基本时钟信号连续延迟的延迟时钟信号。存储装置包括多个存储元件，其中，在施加与基本时钟信号异步的触发信号之后，响应于在相关联的所述基本和延迟的时钟信号中发生的转换，存储其中的预定电平。时钟选择逻辑电路由存储装置的输出信号控制，用于检测在施加异步触发信号时在时间上最近发生的时钟信号转换，并且基于所述时钟信号的结果来选择期望的一个时钟信号检测，作为同步时钟信号输出。

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