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1. 发明授权

US07054990B1 External storage device using non-volatile semiconductor memory 有权
标题翻译：使用非易失性半导体存储器的外部存储设备
公开(公告)号：US07054990B1
公开(公告)日：2006-05-30
申请号：US09635217
申请日：2000-08-10
申请人： Takayuki Tamura , Jun Kitahara , Toru Owada , Shinichi Sawamura , Takeshi Asahi , Nagamasa Mizushima , Takashi Totsuka , Yasushi Akao
发明人： Takayuki Tamura , Jun Kitahara , Toru Owada , Shinichi Sawamura , Takeshi Asahi , Nagamasa Mizushima , Takashi Totsuka , Yasushi Akao
IPC分类号： G06F12/00
CPC分类号： G11C8/20 , G06F12/1466 , G11C7/24 , G11C16/22
摘要： The external storage device according to the present invention which uses a non-volatile semiconductor memory such as a flash memory is provided with plural areas which store user data, and restricts access to the user data from a host computer and also dynamically changes an area an access to which is to be restricted. Accordingly, the ease of use of the external storage device for the host computer is improved. Specifically, the interior of the flash memory is divided into a normal area not protected by a password or the like and a protected area protected by a password or the like. A microprocessor controls accesses to the normal area and the protected area in accordance with a command from the host computer. In addition, the host computer can access the protected area after passing through authentication using a password. Moreover, the host computer changes information indicative of the location of the protected area, thereby dynamically changing the protection area.
摘要翻译：根据本发明的使用诸如闪速存储器的非易失性半导体存储器的外部存储装置设置有存储用户数据的多个区域，并且限制从主计算机访问用户数据，并且还动态地改变区域访问被限制。因此，提高了用于主计算机的外部存储装置的易用性。具体地说，闪速存储器的内部被划分为不受密码等保护的正常区域和由密码等保护的保护区域。微处理器根据主计算机的命令控制对正常区域和保护区域的访问。此外，主机通过使用密码的认证后，可以访问保护区域。此外，主计算机改变指示保护区域的位置的信息，从而动态地改变保护区域。

2. 发明授权

US07100055B2 Information storage system, information transfer system and storage medium thereof 失效
标题翻译：信息存储系统，信息传输系统及其存储介质
公开(公告)号：US07100055B2
公开(公告)日：2006-08-29
申请号：US09943754
申请日：2001-09-04
申请人： Toru Owada , Jun Kitahara , Takeshi Asahi , Takayuki Tamura , Nagamasa Mizushima , Ikuya Kawasaki , Takashi Totsuka
发明人： Toru Owada , Jun Kitahara , Takeshi Asahi , Takayuki Tamura , Nagamasa Mizushima , Ikuya Kawasaki , Takashi Totsuka
IPC分类号： G06F17/00
CPC分类号： G06F21/78
摘要： A storage medium includes a storage device for storing information, information required for encryption and encrypted information, and an I/F device for inputting and outputting information, information required for coding and store encrypted information in a storage device or from an external apparatus other than the storage device, and an encoding device for coding of information and decoding of encoded information. When outputting information stored inside the storage device, information is encoded using encryption key information, and along with obtaining the encoded information and obtaining the encoded encryption key information by using another encryption key. Both the encoded information and encoded encryption key information are output so that decoding the information without the storage medium is impossible.
摘要翻译：存储介质包括用于存储信息的存储装置，用于加密和加密信息所需的信息，以及用于输入和输出信息的I / F装置，用于对存储装置中的加密信息进行编码和存储所需的信息，或者从除外存储装置，以及用于编码信息和编码信息的解码的编码装置。当输出存储在存储装置内的信息时，使用加密密钥信息对信息进行编码，并且获得编码信息并通过使用其他加密密钥获得编码的加密密钥信息。输出编码信息和编码加密密钥信息，使得不存储介质的信息解码是不可能的。

3. 发明授权

US06459644B2 Semiconductor memory device with block alignment function 失效
标题翻译：具有块对准功能的半导体存储器件
公开(公告)号：US06459644B2
公开(公告)日：2002-10-01
申请号：US09779610
申请日：2001-02-09
申请人： Nagamasa Mizushima , Kunihiro Katayama , Kazunori Furusawa , Tomihisa Hatano , Takayuki Tamura
发明人： Nagamasa Mizushima , Kunihiro Katayama , Kazunori Furusawa , Tomihisa Hatano , Takayuki Tamura
IPC分类号： G11C800
CPC分类号： G06F3/0601 , G06F12/0246 , G06F12/04 , G06F2003/0694 , G11C16/349
摘要： In the present invention, disclosed is a semiconductor memory device capable of reducing the number of erasing times of each block allocated to a cluster or the number of blocks to be erased in one writing to the minimum. As an embodiment of the present invention, when a host system 1 performs accessing, for each cluster as a unit, to the FAT partition prepared on a flash memory 17 of the semiconductor memory device 100, a CPU 6 adds an address offset value held by address offset storage section 10 to a logical address specified by the host system 1, whereby a logical address of a head sector of the cluster correspond to a physical address of a head sector of a unit block for erasing/writing data in the flash memory 17.
摘要翻译：在本发明中，公开了一种半导体存储装置，其能够将分配给群集的每个块的擦除次数或一次写入中要擦除的块的数量减少到最小。作为本发明的一个实施例，当主机系统1以每个集群为单位执行对在半导体存储装置100的闪速存储器17上准备的FAT分区的访问时，CPU6将由地址偏移存储部分10分配给由主机系统1指定的逻辑地址，由此簇的头扇区的逻辑地址对应于用于擦除/写入闪速存储器17中的数据的单元块的头扇区的物理地址。

4. 再颁专利

USRE45857E1 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：USRE45857E1
公开(公告)日：2016-01-19
申请号：US13475679
申请日：2012-05-18
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译：一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统，对连续扇区数据的读命令作出响应。

5. 发明授权

US08258318B2 Process for production of coumarin dimer compound 有权
标题翻译：生产香豆素二聚体化合物的方法
公开(公告)号：US08258318B2
公开(公告)日：2012-09-04
申请号：US12451213
申请日：2008-04-28
申请人： Hideo Suzuki , Takayuki Tamura
发明人： Hideo Suzuki , Takayuki Tamura
IPC分类号： C07D311/00
CPC分类号： C07D493/04
摘要： There is provided a one-step process for producing a dihydroxy-substituted coumarin dimer compound by a photodimerization reaction of a hydroxy-substituted coumarin compound. The process comprises subjecting a hydroxy-substituted coumarin compound to a photodimerization reaction in a solvent selected from aliphatic ketones having 3 to 10 carbon atoms, aliphatic carboxylic acid esters having 2 to 10 carbon atoms, aliphatic alcohols having 1 to 10 carbon atoms, aliphatic nitriles having 2 to 10 carbon atoms, ethers having 4 to 10 carbon atoms, amides having 3 to 10 carbon atoms, and a mixture thereof to obtain a dihydroxy-substituted coumarin dimer compound.
摘要翻译：提供了通过羟基取代的香豆素化合物的光二聚反应制备二羟基取代的香豆素二聚体化合物的一步法。该方法包括使羟基取代的香豆素化合物在选自具有3至10个碳原子的脂族酮，2至10个碳原子的脂肪族羧酸酯，1至10个碳原子的脂族醇，脂族醇，脂族腈具有2至10个碳原子，具有4至10个碳原子的醚，具有3至10个碳原子的酰胺及其混合物，以获得二羟基取代的香豆素二聚体化合物。

6. 发明授权

US08064257B2 Semiconductor memory device having faulty cells 有权
标题翻译：具有故障单元的半导体存储器件
公开(公告)号：US08064257B2
公开(公告)日：2011-11-22
申请号：US12615502
申请日：2009-11-10
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C11/34
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

7. 发明申请

US20090292103A1 POLYAMIC ACID AND POLYIMIDE 有权
标题翻译：聚氨酯和聚酰亚胺
公开(公告)号：US20090292103A1
公开(公告)日：2009-11-26
申请号：US12373230
申请日：2007-07-09
申请人： Hideo Suzuki , Takayuki Tamura , Yoshikazu Ootsuka
发明人： Hideo Suzuki , Takayuki Tamura , Yoshikazu Ootsuka
IPC分类号： C08G73/10 , C07C61/04 , C07D307/77
CPC分类号： C08G73/1078 , C07D487/04 , C07D493/04 , C08G73/1046 , C08G73/105 , C08G73/1075 , C08L79/08
摘要： A polyamic acid comprising at least 10 mol % repeating units represented by the formula [1] or [2]; and a polyimide represented by the formula [3] or [4] which is obtained from the polyamic acid. A polyimide film having high heat resistance and satisfactory in light-transmitting properties and tensile strength is obtained from the polyamic acid. (In the formulae, R1 and R2 each independently represents hydrogen or C1-10 alkyl; R3 and R4 each independently represents hydrogen, halogeno, C1-10alkyl, or phenyl or the R3 and R4 on adjoining carbon atoms are bonded to each other to form C3-8 cycloalkyl or phenyl; R5 represents a divalent organic group; and n is an integer of 2 or larger.)
摘要翻译：包含由式[1]或[2]表示的至少10摩尔％重复单元的聚酰胺酸; 和由聚酰胺酸得到的由式[3]或[4]表示的聚酰亚胺。从聚酰胺酸得到耐热性高，透光性和拉伸强度良好的聚酰亚胺膜。（式中，R 1和R 2各自独立地表示氢或C 1-10烷基; R 3和R 4各自独立地表示氢，卤素，C 1-10烷基或苯基，或者相邻碳原子上的R 3和R 4彼此键合形成 C3-8环烷基或苯基; R5表示二价有机基团; n为2以上的整数。）

8. 发明申请

US20090052377A1 MOBILE COMMUNICATION TERMINAL, COMMUNICATION APPARATUS, MOBILE COMMUNICATION METHOD, AND COMMUNICATION METHOD 有权
标题翻译：移动通信终端，通信设备，移动通信方法和通信方法
公开(公告)号：US20090052377A1
公开(公告)日：2009-02-26
申请号：US12189431
申请日：2008-08-11
申请人： Hosei Matsuoka , Takayuki Tamura
发明人： Hosei Matsuoka , Takayuki Tamura
IPC分类号： H04W80/00 , H04W88/06 , H04W88/10
CPC分类号： H04W36/28 , H04L69/14 , H04L69/324 , H04W36/36
摘要： An object of the present invention is to make it possible to appropriately maintain PPP-based communications even in an environment in which the terminal moves and the communication environment continually changes. A mobile communication terminal comprises a plurality of wireless accessing means for establishing PPP-based communication links for respectively different modes of wireless communications with a fixed communication apparatus, which is a communication partner; a PPP device for combining the established communication links; and a valid wireless LAN searching portion for detecting that wireless communication is possible for a wireless LAN adapter. The PPP device executes control so as to establish communication links for the wireless LAN adapter detected as being capable of wireless communication, and for a L2TP virtual device.
摘要翻译：本发明的目的在于，即使在终端移动的环境和通信环境持续变化的情况下，也可以适当地维护基于PPP的通信。移动通信终端包括：多个无线接入装置，用于分别与作为通信伙伴的固定通信装置的不同模式的无线通信建立基于PPP的通信链路; 用于组合建立的通信链路的PPP设备; 以及用于检测无线LAN适配器的无线通信的有效的无线LAN搜索部分。 PPP设备执行控制，以建立被检测为能够进行无线通信的无线LAN适配器和L2TP虚拟设备的通信链路。

9. 发明授权

US07269748B2 System for preventing errors upon ejection of a memory card from a slot 有权
标题翻译：用于在从存储卡弹出存储卡时防止错误的系统
公开(公告)号：US07269748B2
公开(公告)日：2007-09-11
申请号：US10712996
申请日：2003-11-17
申请人： Shinichi Shuto , Takayuki Tamura , Chiaki Kumahara
发明人： Shinichi Shuto , Takayuki Tamura , Chiaki Kumahara
IPC分类号： G06F1/00 , G06F13/00 , H05K7/10
CPC分类号： G06F1/305
摘要： Disclosed herewith is a semiconductor processing system such as a card type electronic device, which can easily cope with an error caused by power shutoff that occurs when the card is ejected. The semiconductor processing system is provided with an interface control circuit and a processing circuit and receives operation power from an external device such as a card slot when it is inserted therein. According to a first aspect of the present invention for coping with an error caused by power shutoff that occurs when the card is ejected, the interface control circuit, when the card is ejected from the card slot, detects a potential change to occur at a first external terminal to be disconnected from a predetermined terminal of the card slot before the power supply from the card slot is shut off, then instructs the processing circuit that is active to perform an ending processing. The semiconductor processing system can end the processing by itself before the power supply stops completely.
摘要翻译：这里公开了一种诸如卡型电子设备的半导体处理系统，其可以容易地处理当卡被弹出时发生的由电源关闭引起的错误。半导体处理系统设置有接口控制电路和处理电路，并且当插入其中时从诸如卡槽的外部设备接收操作电力。根据本发明的第一方面，为了应对当卡被弹出时发生的由电源关闭引起的错误，当卡从卡插槽中弹出时，接口控制电路检测到第一次发生的潜在变化在从卡槽供电之前将外部终端从卡槽的预定终端断开，然后指示有效的处理电路执行结束处理。在电源完全停止之前，半导体处理系统可以自己结束处理。

10. 发明申请

US20070101237A1 Memory card and memory controller 有权
标题翻译：存储卡和存储控制器
公开(公告)号：US20070101237A1
公开(公告)日：2007-05-03
申请号：US11504016
申请日：2006-08-15
申请人： Takayuki Tamura , Hirofumi Shibuya , Hiroyuki Goto , Shigemasa Shiota
发明人： Takayuki Tamura , Hirofumi Shibuya , Hiroyuki Goto , Shigemasa Shiota
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G06F11/1068 , G06F13/1673 , G11C5/04 , G11C29/72 , G11C2029/0409
摘要： A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.
摘要翻译：存储卡具有多个非易失性存储器和用于控制非易失性存储器的操作的主控制器。主控制器响应于外部访问指令对非易失性存储器执行访问控制，以及用于将非易失性存储器的访问错误相关存储区域与其他存储区域交替的替代控制。在访问控制中，通过使多个非易失性存储器并行访问操作来实现闪速存储器之间的数据传输的加速。在交替控制中，对于发生访问错误的每个非易失性存储器，存储区域被替代。

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