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1. 发明授权

US07902030B2 Manufacturing method for semiconductor device and semiconductor device 失效
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US07902030B2
公开(公告)日：2011-03-08
申请号：US12483728
申请日：2009-06-12
申请人： Takayuki Ito , Yusuke Oshiki , Kouji Matsuo , Kenichi Yoshino , Takaharu Itani , Takuo Ohashi , Toshihiko Iinuma , Kiyotaka Miyano , Kunihiro Miyazaki
发明人： Takayuki Ito , Yusuke Oshiki , Kouji Matsuo , Kenichi Yoshino , Takaharu Itani , Takuo Ohashi , Toshihiko Iinuma , Kiyotaka Miyano , Kunihiro Miyazaki
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/2686 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp(21541/T).
摘要翻译：一种半导体装置的制造方法，其特征在于，在半导体基板的由第一原子构成的表面上形成有与半导体基板的表面的面积为5〜30％的开口率y的开口的开口部; 在所述开口中形成外延层，所述外延层由含有15〜25％的浓度的第二原子的混合晶体构成，所述第二原子的晶格常数不同于所述第一原子的晶格常数; 将杂质离子注入到外延层中; 并在预定温度T下进行活化退火，预定温度T等于或高于1150℃，并且满足y＆nlE; 1E-5exp（21541 / T）的关系。

2. 发明申请

US20090309133A1 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US20090309133A1
公开(公告)日：2009-12-17
申请号：US12483728
申请日：2009-06-12
申请人： Takayuki Ito , Yusuke Oshiki , Kouji Matsuo , Kenichi Yoshino , Takaharu Itani , Takuo Ohashi , Toshihiko Iinuma , Kiyotaka Miyano , Kunihiro Miyazaki
发明人： Takayuki Ito , Yusuke Oshiki , Kouji Matsuo , Kenichi Yoshino , Takaharu Itani , Takuo Ohashi , Toshihiko Iinuma , Kiyotaka Miyano , Kunihiro Miyazaki
IPC分类号： H01L29/04 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/2686 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp(21541/T).
摘要翻译：一种半导体装置的制造方法，其特征在于，在半导体基板的由第一原子构成的表面上形成有与半导体基板的表面的面积为5〜30％的开口率y的开口的开口部; 在所述开口中形成外延层，所述外延层由含有15〜25％的浓度的第二原子的混合晶体构成，所述第二原子的晶格常数不同于所述第一原子的晶格常数; 将杂质离子注入到外延层中; 并在预定温度T下进行活化退火，预定温度T等于或高于1150℃，并且满足y <= 1E-5exp（21541 / T）的关系。

3. 发明授权

US08148717B2 Manufacturing method for semiconductor device and semiconductor device 失效
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US08148717B2
公开(公告)日：2012-04-03
申请号：US12929504
申请日：2011-01-28
申请人： Takayuki Ito , Yusuke Oshiki , Kouji Matsuo , Kenichi Yoshino , Takaharu Itani , Takuo Ohashi , Toshihiko Iinuma , Kiyotaka Miyano , Kunihiro Miyazaki
发明人： Takayuki Ito , Yusuke Oshiki , Kouji Matsuo , Kenichi Yoshino , Takaharu Itani , Takuo Ohashi , Toshihiko Iinuma , Kiyotaka Miyano , Kunihiro Miyazaki
IPC分类号： H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L21/823807 , H01L21/2686 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp (21541/T).
摘要翻译：一种半导体装置的制造方法，其特征在于，在半导体基板的由第一原子构成的表面上形成有与半导体基板的表面的面积为5〜30％的开口率y的开口的开口部; 在所述开口中形成外延层，所述外延层由含有15〜25％的浓度的第二原子的混合晶体构成，所述第二原子的晶格常数不同于所述第一原子的晶格常数; 将杂质离子注入到外延层中; 并在预定温度T下进行活化退火，预定温度T等于或高于1150℃，并且满足y＆nlE; 1E-5exp（21541 / T）的关系。

4. 发明申请

US20110127578A1 Manufacturing method for semiconductor device and semiconductor device 失效
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US20110127578A1
公开(公告)日：2011-06-02
申请号：US12929504
申请日：2011-01-28
申请人： Takayuki Ito , Yusuke Oshiki , Kouji Matsuo , Kenichi Yoshino , Takaharu Itani , Takuo Ohashi , Toshihiko Iinuma , Kiyotaka Miyano , Kunihiro Miyazaki
发明人： Takayuki Ito , Yusuke Oshiki , Kouji Matsuo , Kenichi Yoshino , Takaharu Itani , Takuo Ohashi , Toshihiko Iinuma , Kiyotaka Miyano , Kunihiro Miyazaki
IPC分类号： H01L29/12
CPC分类号： H01L21/823807 , H01L21/2686 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp (21541/T).
摘要翻译：一种半导体装置的制造方法，其特征在于，在半导体基板的由第一原子构成的表面上形成有与半导体基板的表面的面积为5〜30％的开口率y的开口的开口部; 在所述开口中形成外延层，所述外延层由含有15〜25％的浓度的第二原子的混合晶体构成，所述第二原子的晶格常数不同于所述第一原子的晶格常数; 将杂质离子注入到外延层中; 并在预定温度T下进行活化退火，预定温度T等于或高于1150℃，并且满足y＆nlE; 1E-5exp（21541 / T）的关系。

5. 发明申请

US20080268660A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080268660A1
公开(公告)日：2008-10-30
申请号：US12108589
申请日：2008-04-24
申请人： Takaharu Itani , Kenichi Yoshino , Takayuki Ito , Takashi Kawakami , Tetsuya Kugimiya
发明人： Takaharu Itani , Kenichi Yoshino , Takayuki Ito , Takashi Kawakami , Tetsuya Kugimiya
IPC分类号： H01L21/02 , H01L21/00
CPC分类号： H01L21/02087 , H01L21/26513 , H01L21/2686 , H01L21/67115 , H01L29/66575
摘要： A method of manufacturing a semiconductor device that involves a heat treatment of a semiconductor substrate, has removing a superficial layer from an upper surface of an edge part of said semiconductor substrate, a bevel surface of the edge part of said semiconductor substrate and a side surface of the edge part of said semiconductor substrate; and conducting the heat treatment of said semiconductor substrate by irradiating said semiconductor substrate with light having a pulse width of 0.1 milliseconds to 100 milliseconds from a light source after said superficial layer is removed.
摘要翻译：制造涉及半导体衬底的热处理的半导体器件的方法，从所述半导体衬底的边缘部分的上表面，所述半导体衬底的边缘部分的斜面以及侧表面的所述半导体衬底的边缘部分; 以及在去除所述表面层之后，从光源照射具有0.1毫秒至100毫微秒的脉冲宽度的光，从而对所述半导体衬底进行热处理。

6. 发明授权

US08101974B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08101974B2
公开(公告)日：2012-01-24
申请号：US12328551
申请日：2008-12-04
申请人： Hiroshi Ohno , Takaharu Itani , Eiji Morifuji , Norikazu Ooishi , Toshihiko Iinuma , Yoshinori Honguh
发明人： Hiroshi Ohno , Takaharu Itani , Eiji Morifuji , Norikazu Ooishi , Toshihiko Iinuma , Yoshinori Honguh
IPC分类号： H01L27/10 , H01L29/76 , H01L29/94 , H01L23/48 , H01L23/52
CPC分类号： H01L21/2686 , H01L21/268 , H01L21/823437 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 μm or less includes a circuit pattern region formed on a semiconductor substrate, and a dummy pattern region formed separately from the circuit pattern region on the semiconductor substrate. The circuit pattern region has an integrated circuit pattern containing a gate pattern related to a circuit operation. The dummy pattern region has dummy gate patterns that have the same structure as that of a gate pattern used in the integrated circuit pattern and the dummy gate patterns are repeatedly arranged with a pitch 0.4 times or less the principal wavelength.
摘要翻译：通过主要波长为1.5μm或更小的辐射光进行光学退火处理的半导体器件包括形成在半导体衬底上的电路图案区域和与半导体衬底上的电路图案区域分开形成的虚设图案区域。电路图案区域具有包含与电路操作相关的栅极图案的集成电路图案。伪图案区域具有与集成电路图案中使用的栅极图案相同的结构的伪栅极图案，并且虚设栅极图案以主要波长的0.4倍或更小的间距重复排列。

7. 发明申请

US20090146310A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090146310A1
公开(公告)日：2009-06-11
申请号：US12328551
申请日：2008-12-04
申请人： Hiroshi Ohno , Takaharu Itani , Eiji Morifuji , Norikazu Ooishi , Toshihiko Iinuma , Yoshinori Honguh
发明人： Hiroshi Ohno , Takaharu Itani , Eiji Morifuji , Norikazu Ooishi , Toshihiko Iinuma , Yoshinori Honguh
IPC分类号： H01L23/48 , H01L21/3205
CPC分类号： H01L21/2686 , H01L21/268 , H01L21/823437 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 μm or less includes a circuit pattern region formed on a semiconductor substrate, and a dummy pattern region formed separately from the circuit pattern region on the semiconductor substrate. The circuit pattern region has an integrated circuit pattern containing a gate pattern related to a circuit operation. The dummy pattern region has dummy gate patterns that have the same structure as that of a gate pattern used in the integrated circuit pattern and the dummy gate patterns are repeatedly arranged with a pitch 0.4 times or less the principal wavelength.
摘要翻译：通过主要波长为1.5μm或更小的辐射光进行光学退火处理的半导体器件包括形成在半导体衬底上的电路图案区域和与半导体衬底上的电路图案区域分开形成的虚设图案区域。电路图案区域具有包含与电路操作相关的栅极图案的集成电路图案。伪图案区域具有与集成电路图案中使用的栅极图案相同的结构的伪栅极图案，并且虚设栅极图案以主要波长的0.4倍或更小的间距重复排列。

8. 发明授权

US07279405B2 Fabrication method for semiconductor device and manufacturing apparatus for the same 有权
标题翻译：半导体装置及其制造装置的制造方法
公开(公告)号：US07279405B2
公开(公告)日：2007-10-09
申请号：US10980232
申请日：2004-11-04
申请人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
发明人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/425
CPC分类号： H01L21/26533 , H01L21/324 , H01L29/6659
摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion maybe controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.
摘要翻译：通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。通过光照射进行杂质掺杂后的退火。这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射。杂质扩散可以被控制到最小，并且当在MOSFET的源极和漏极延伸区域中形成离子注入层时，在杂质掺杂过程中已经发展出的晶体缺陷可以被充分地减小，或者源中的离子注入层和漏区。

9. 发明申请

US20080260501A1 Fabrication method for semiconductor device and manufacturing apparatus for the same 有权
标题翻译：半导体装置及其制造装置的制造方法
公开(公告)号：US20080260501A1
公开(公告)日：2008-10-23
申请号：US11819776
申请日：2007-06-29
申请人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
发明人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/677
CPC分类号： H01L21/26533 , H01L21/324 , H01L29/6659
摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.
摘要翻译：通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。通过光照射进行杂质掺杂后的退火。通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活这些杂质。除了使用闪光灯FLA的最终光照射之外，光辐射的特征在于使用W卤素灯RTA或闪光灯FLA。杂质扩散可以被控制到最小，并且当在源的源极和漏极延伸区域中形成离子注入层或在源中的离子注入层形成离子注入层时，可以充分减少在杂质掺杂过程中发展的晶体缺陷，以及漏极区域。

10. 发明申请

US20070243701A1 Semiconductor device fabrication method using ultra-rapid thermal annealing 审中-公开
标题翻译：半导体器件制造方法采用超快速热退火
公开(公告)号：US20070243701A1
公开(公告)日：2007-10-18
申请号：US11783035
申请日：2007-04-05
申请人： Takayuki Ito , Kyoichi Suguro , Takaharu Itani , Yoshihiko Saito
发明人： Takayuki Ito , Kyoichi Suguro , Takaharu Itani , Yoshihiko Saito
IPC分类号： H01L21/425
CPC分类号： H01L21/2686 , H01L21/324 , H01L29/7833 , H01L29/7842
摘要： An impurity is ion-implanted into the major surface of an Si substrate having a bulk microdefect density of 5×106 to 5×107 cm−3, a bulk microdefect size smaller than 100 nm, and a dissolved oxygen concentration of 1.1×1018 to 1.2×1018 cm−3. The Si substrate then undergoes ultra-rapid thermal annealing whose heating/cooling rate is higher than 1×105° C./sec, thereby electrically activating the impurity to form at least a partial impurity diffusion layer of a semiconductor element.
摘要翻译：将杂质离子注入到具有体积微密度为5×10 -6至5×10 -7 cm -3以下的Si衬底的主表面中，体积微观尺寸小于100nm，溶解氧浓度为1.1×10 18至1.2×10 -8 cm -3。然后，Si衬底经历其加热/冷却速率高于1×10 5℃/秒的超快速热退火，从而电激活杂质以形成半导体的至少部分杂质扩散层元件。

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