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1. 发明申请

US20060095975A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060095975A1
公开(公告)日：2006-05-04
申请号：US11212585
申请日：2005-08-29
申请人： Takayoshi Yamada , Shinzo Koyama , Yoshihisa Kato , Yasuhiro Shimada
发明人： Takayoshi Yamada , Shinzo Koyama , Yoshihisa Kato , Yasuhiro Shimada
IPC分类号： H04L9/32
CPC分类号： G06F21/79 , H04L9/085
摘要： A semiconductor device of the present invention includes: at least one of non-volatile memory unit operable to store data; at least one of an arithmetic-logic unit operable to perform an arithmetic-logic operation using data which is stored in the memory unit and data that is inputted from outside; and an output unit operable to output a result of arithmetic-logic operation performed by the arithmetic-logic unit; wherein the memory unit, the arithmetic-logic unit, and the output unit are included in a functional block, and an output line of each of the memory unit is connected only to one of at least one of the arithmetic-logic unit.
摘要翻译：本发明的半导体器件包括：用于存储数据的非易失性存储单元中的至少一个; 算术逻辑单元中的至少一个，其可操作以使用存储在存储单元中的数据和从外部输入的数据执行算术运算; 以及输出单元，其可操作以输出由所述算术单元执行的算术逻辑运算的结果; 其中所述存储器单元，所述算术逻辑单元和所述输出单元包括在功能块中，并且所述存储器单元中的每一个的输出线仅与所述算术单元中的至少一个连接。

2. 发明授权

US06618284B2 Semiconductor memory and method for driving the same 失效
公开(公告)号：US06618284B2
公开(公告)日：2003-09-09
申请号：US10011489
申请日：2001-12-11
申请人： Yasuhiro Shimada , Yoshihisa Kato , Takayoshi Yamada
发明人： Yasuhiro Shimada , Yoshihisa Kato , Takayoshi Yamada
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A semiconductor memory includes a ferroelectric capacitor having a ferroelectric film, a first electrode formed on the ferroelectric film and a second electrode formed under the ferroelectric film. A data writing unit causes a first state in which the ferroelectric film has polarization in a direction from the first electrode to the second electrode or in a direction from the second electrode to the first electrode and has a substantially saturated polarization value or a second state in which the ferroelectric film has polarization in the same direction as in the first state and has a substantially zero polarization value, thereby writing a data corresponding to the first state or the second state in the ferroelectric capacitor. A data reading unit detects whether the ferroelectric capacitor is in the first state or in the second state, thereby reading a data stored in the ferroelectric capacitor.

3. 发明授权

US06950327B2 Semiconductor memory device and electronic apparatus mounting the same 失效
标题翻译：半导体存储器件和安装它的电子设备
公开(公告)号：US06950327B2
公开(公告)日：2005-09-27
申请号：US10686583
申请日：2003-10-17
申请人： Yasuhiro Shimada , Yoshihisa Kato , Takayoshi Yamada
发明人： Yasuhiro Shimada , Yoshihisa Kato , Takayoshi Yamada
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： In a ferroelectric capacitor, two displacements (points b and c) of a remanent polarization correspond to data “1” and one displacement (point a) of the remanent polarization corresponds to data “0”. When the data “1” is written, either of two electric voltage pulses different in potential or in pulse width is applied to the ferroelectric capacitor to position the displacement of the remanent polarization in the ferroelectric capacitor at the point b or at the point c. When the data “0” is written, on the other hand, the displacement of the remanent polarization in the ferroelectric capacitor is positioned at the point a.
摘要翻译：在铁电电容器中，剩余极化的两个位移（点b和c）对应于数据“1”，剩余极化的一个位移（点a）对应于数据“0”。当写入数据“1”时，电压或脉冲宽度不同的两个电压脉冲中的任一个施加到铁电电容器，以将铁电电容器中剩余极化的位移定位在点b处或点c处。另一方面，当写入数据“0”时，铁电电容器中剩余极化的位移位于点a处。

4. 发明授权

US06853576B2 Semiconductor device, method for fabricating the same, and method for driving the same 失效
标题翻译：半导体装置及其制造方法及其驱动方法
公开(公告)号：US06853576B2
公开(公告)日：2005-02-08
申请号：US10653201
申请日：2003-09-03
申请人： Yoshihisa Kato , Yasuhiro Shimada , Takayoshi Yamada
发明人： Yoshihisa Kato , Yasuhiro Shimada , Takayoshi Yamada
IPC分类号： G11C7/10 , G11C7/12 , G11C11/22
CPC分类号： G11C11/22 , G11C7/1048 , G11C7/12
摘要： A semiconductor memory device has a plurality of memory cells each having a first ferroelectric capacitor for storing data as a polarization value. First voltage applying means applies a first read voltage between the pair of electrodes of the first ferroelectric capacitor composing that one of the plurality of memory cells from which data is to be read. Data reading means detects the polarization value in the first ferroelectric capacitor when the first read voltage is applied between the pair of electrodes of the first ferroelectric capacitor and thereby reads the data stored in the first ferroelectric capacitor therefrom. A hysteresis loop in the first ferroelectric capacitor is shifted in a direction of voltage opposite in polarity to the first read voltage.
摘要翻译：半导体存储器件具有多个存储单元，每个存储单元具有用于存储数据作为极化值的第一铁电电容器。第一电压施加装置在构成要从其读取数据的多个存储单元中的一个的第一强电介质电容器的一对电极之间施加第一读取电压。当在第一强电介质电容器的一对电极之间施加第一读取电压时，数据读取装置检测第一铁电电容器中的极化值，从而读取存储在第一铁电电容器中的数据。第一铁电电容器中的磁滞回线在与第一读取电压的极性相反的电压方向上偏移。

5. 发明授权

US06693840B2 Non-volatile semiconductor memory device with enhanced erase/write cycle endurance 失效
标题翻译：具有增强的擦除/写入周期耐久性的非易失性半导体存储器件
公开(公告)号：US06693840B2
公开(公告)日：2004-02-17
申请号：US10271139
申请日：2002-10-15
申请人： Yasuhiro Shimada , Yoshihisa Kato , Takayoshi Yamada
发明人： Yasuhiro Shimada , Yoshihisa Kato , Takayoshi Yamada
IPC分类号： G11C700
CPC分类号： G11C14/00 , G11C16/30
摘要： The power-supply unit, while directing externally supplied power to the control unit and the like, accumulates an amount of power that is required by the control unit to save data from the volatile memory to the non-volatile memory. When an external power supply has started, the control unit restores data of the non-volatile memory in the volatile memory; and when the external power supply has stopped, the control unit saves data from the volatile memory to the non-volatile memory.
摘要翻译：电源单元在向控制单元等引导外部供电的同时，累积控制单元所需的功率量，以将数据从易失性存储器保存到非易失性存储器。当外部电源开始时，控制单元恢复易失性存储器中的非易失性存储器的数据; 并且当外部电源停止时，控制单元将数据从易失性存储器保存到非易失性存储器。

6. 发明授权

US06707704B2 Semiconductor memory device and drive method therefor 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US06707704B2
公开(公告)日：2004-03-16
申请号：US10392843
申请日：2003-03-21
申请人： Yoshihisa Kato , Yasuhiro Shimada , Takayoshi Yamada
发明人： Yoshihisa Kato , Yasuhiro Shimada , Takayoshi Yamada
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： The semiconductor memory device of the invention includes at least three memory cell blocks arranged in a word line direction. Each of the memory cell blocks includes a plurality of memory cells arranged in a bit line direction. Each of the memory cells includes a ferroelectric capacitor for storing data by displacement of polarization of a ferroelectric film and a selection transistor connected to one of paired electrodes of the ferroelectric capacitor. Each of the memory cell blocks also includes: a bit line, a sub-bit line and a source line extending in the bit line direction; and a read transistor having a gate connected to one end of the sub-bit line, a source connected to the source line, and a drain connected to one end of the bit line. The read transistor reads data by detecting the displacement of the polarization of the ferroelectric film of the ferroelectric capacitor of a data read memory cell from which data is read among the plurality of memory cells. The sub-bit lines of any two of the memory cell blocks are connected to each other via a sub-bit line coupling switch.
摘要翻译：本发明的半导体存储器件包括沿字线方向布置的至少三个存储单元块。每个存储单元块包括以位线方向排列的多个存储单元。每个存储单元包括用于通过铁电薄膜的极化位移存储数据的铁电电容器和连接到铁电体电容器的一对电极之一的选择晶体管。每个存储单元块还包括：位线，子位线和沿位线方向延伸的源极线; 以及读取晶体管，其具有连接到子位线的一端的栅极，连接到源极线的源极和连接到位线的一端的漏极。读取晶体管通过检测在多个存储单元中从其读取数据的数据读取存储单元的铁电电容器的铁电体的极化的位移来读取数据。任何两个存储单元块的子位线通过子位线耦合开关相互连接。

7. 发明申请

US20080024206A1 Noise reduction circuit 有权
标题翻译：降噪电路
公开(公告)号：US20080024206A1
公开(公告)日：2008-01-31
申请号：US11826582
申请日：2007-07-17
申请人： Takahiko Murata , Takumi Yamaguchi , Shinzo Koyama , Shigetaka Kasuga , Takayoshi Yamada
发明人： Takahiko Murata , Takumi Yamaguchi , Shinzo Koyama , Shigetaka Kasuga , Takayoshi Yamada
IPC分类号： H03K5/00
CPC分类号： H03K5/1252 , H04N5/21
摘要： A noise reduction circuit receives, as an input signal, a voltage difference between two different signals. The noise reduction circuit includes: an amplifier circuit for amplifying the two different signals; a voltage difference detection circuit for detecting a voltage difference between the two different signals amplified by the amplifier circuit; and an electric charge accumulation circuit section or a voltage adding circuit. The electric charge accumulation circuit section accumulates, a predetermined number of times, an electric charge corresponding to the voltage difference detected by the voltage difference detection circuit and combines the accumulated electric charges to output the resultant electric charge. The voltage adding circuit adds, a predetermined number of times, the voltage difference detected by the voltage difference detection circuit.
摘要翻译：噪声降低电路作为输入信号接收两个不同信号之间的电压差。噪声降低电路包括：用于放大两个不同信号的放大器电路; 用于检测由放大器电路放大的两个不同信号之间的电压差的电压差检测电路; 和电荷累积电路部分或电压相加电路。电荷累积电路部分累积与由电压差检测电路检测出的电压差对应的电荷的预定次数，并组合累计的电荷以输出所得的电荷。电压加法电路将电压差检测电路检测出的电压差加上规定次数。

8. 发明授权

US07589585B2 Noise reduction circuit 有权
标题翻译：降噪电路
公开(公告)号：US07589585B2
公开(公告)日：2009-09-15
申请号：US11826582
申请日：2007-07-17
申请人： Takahiko Murata , Takumi Yamaguchi , Shinzo Koyama , Shigetaka Kasuga , Takayoshi Yamada
发明人： Takahiko Murata , Takumi Yamaguchi , Shinzo Koyama , Shigetaka Kasuga , Takayoshi Yamada
IPC分类号： H03K17/16 , H03K5/00
CPC分类号： H03K5/1252 , H04N5/21
摘要： A noise reduction circuit outputs a signal corresponding to a voltage difference between two different signals. The noise reduction circuit includes: an amplifier circuit for amplifying the two different signals at different timings; and a voltage difference detection circuit for detecting a voltage difference between the two different signals amplified by the amplifier circuit. The noise reduction circuit accumulates, a predetermined number of times, an electric charge corresponding to the voltage difference detected by the voltage difference detection circuit and combines the accumulated electric charges to output a resultant electric charge.
摘要翻译：噪声降低电路输出与两个不同信号之间的电压差对应的信号。噪声降低电路包括：放大器电路，用于在不同的定时放大两个不同的信号; 以及电压差检测电路，用于检测由放大器电路放大的两个不同信号之间的电压差。噪声降低电路以预定次数累积与由电压差检测电路检测出的电压差对应的电荷，并组合累积的电荷以输出所得的电荷。

9. 发明授权

US07956916B2 Solid-state imaging device 有权
标题翻译：固态成像装置
公开(公告)号：US07956916B2
公开(公告)日：2011-06-07
申请号：US12195584
申请日：2008-08-21
申请人： Takahiko Murata , Yoshihisa Kato , Shigetaka Kasuga , Takayoshi Yamada
发明人： Takahiko Murata , Yoshihisa Kato , Shigetaka Kasuga , Takayoshi Yamada
IPC分类号： H04N5/335
CPC分类号： H04N5/37452 , H04N5/35581 , H04N5/3559
摘要： Provided is a solid-state imaging device having pixel units that are two-dimensionally arranged, and including: a photodiode that generates an optical signal charge corresponding to an intensity and an exposure time of light; a MOS transistor that transfers the optical signal charge; an accumulating unit that generates a voltage corresponding to the signal charge through the MOS transistor; a storing unit that stores a voltage corresponding to an optical signal charge in the accumulating unit; and a voltage setting unit that sets a value of a voltage in the accumulating unit to a value corresponding to the voltage in the storing unit.
摘要翻译：提供一种具有二维排列的像素单元的固态成像装置，包括：产生对应于光的强度和曝光时间的光信号电荷的光电二极管; 传输光信号电荷的MOS晶体管; 累积单元，其产生对应于通过MOS晶体管的信号电荷的电压; 存储单元，其将与所述积累单元中的光信号电荷相对应的电压存储; 以及电压设定单元，其将所述累积单元中的电压值设定为与所述存储单元中的电压对应的值。

10. 发明授权

US07791524B2 Solid-state imaging device, semiconductor integrated circuit, and signal processing method 有权
标题翻译：固态成像装置，半导体集成电路和信号处理方法
公开(公告)号：US07791524B2
公开(公告)日：2010-09-07
申请号：US12388105
申请日：2009-02-18
申请人： Shigetaka Kasuga , Yoshihisa Kato , Takahiko Murata , Takayoshi Yamada
发明人： Shigetaka Kasuga , Yoshihisa Kato , Takahiko Murata , Takayoshi Yamada
IPC分类号： H03M1/12
CPC分类号： H04N5/378 , H04N5/3742
摘要： A solid-state imaging device includes: pixel circuits arranged in a matrix which perform photoelectric conversion on received light; and an AD conversion unit converting the resultant signal voltage of the photoelectric conversion. The AD conversion unit includes: a reference voltage generation unit generating plural reference voltages which are different from each other within a possible range for a signal voltage; a most significant bit conversion unit that identifies a voltage section including the signal voltage from among the voltage sections each having a corresponding one of the reference voltages as a base point and determines the identified result as the value of the most significant bit of the digital signal; and a least significant bit conversion unit that converts, into the least significant bit of the digital signal, the difference voltage between the signal voltage and the reference voltage as the base point of the identified voltage section.
摘要翻译：固态成像装置包括：以接收光进行光电转换的矩阵状的像素电路; 以及转换所得到的光电转换信号电压的AD转换单元。 AD转换单元包括：在信号电压的可能范围内产生彼此不同的多个参考电压的参考电压产生单元; 一个最高有效位转换单元，其识别包括每个具有对应的一个参考电压的电压部分中的信号电压的电压部分作为基点，并将所识别的结果确定为数字信号的最高有效位的值 ; 以及最低有效位转换单元，其将所述信号电压和所述参考电压之间的差电压转换为所述数字信号的最低有效位作为所识别的电压部分的基点。

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