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1. 发明授权

US07307313B2 Semiconductor device including a vertical field effect transistor, having trenches, and a diode 有权
标题翻译：包括具有沟槽的垂直场效应晶体管和二极管的半导体器件
公开(公告)号：US07307313B2
公开(公告)日：2007-12-11
申请号：US11206212
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Kumar Malhan
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Kumar Malhan
IPC分类号： H01L29/76
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/8083
摘要： A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.
摘要翻译：半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽，沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管，在第二沟槽之间的第二表面上形成的结。

2. 发明授权

US06909155B2 Semiconductor on insulator device 有权
标题翻译：半导体绝缘体器件
公开(公告)号：US06909155B2
公开(公告)日：2005-06-21
申请号：US10101162
申请日：2002-03-20
申请人： Takasumi Ohyanagi , Atsuo Watanabe
发明人： Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/331 , H01L21/336 , H01L21/762 , H01L21/77 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L21/84 , H01L27/06 , H01L27/08 , H01L27/12 , H01L29/08 , H01L29/10 , H01L29/73 , H01L29/78 , H01L29/786 , H04M3/00 , H04M3/18
CPC分类号： H01L29/66681 , G09G3/28 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/1083 , H01L29/66265 , H01L29/66674 , H01L29/7317 , H01L29/7824 , H04M3/005 , H04M3/18 , H04M2201/06
摘要： An N-channel MOS field-effect transistor on an SOI substrate including a source electrode, drain and gate electrodes both disposed via a field oxide film, a gate oxide film, a high concentration P-type layer, a high concentration N-type layer contacting the source electrode and the gate oxide film, a high concentration N-type layer contacting the drain electrode, a p-body layer contacting the high concentration P-type and N-type layers and the gate oxide film. In this transistor, an N-type layer with a concentration higher than that of a drain region contacting the p-body layer constitutes a region covering at most 95% of the source-drain distance. Further, an N-type region having a concentration from 3×1016/cm3 to 1×1022/cm3 is provided near a buried oxide film under the drain electrode.
摘要翻译：在SOI衬底上的N沟道MOS场效应晶体管，其包括经由场氧化膜设置的源电极，漏极和栅电极，栅极氧化膜，高浓度P型层，高浓度N型层与源电极和栅极氧化膜接触，接触漏电极的高浓度N型层，与高浓度P型和N型层接触的p体层和栅氧化膜。在该晶体管中，具有高于与p体层接触的漏极区域的浓度的N型层构成覆盖源极 - 漏极距离的至多95％的区域。此外，浓度为3×10 16 / cm 3至1×10 22 / cm 3的N型区域设置在漏电极下方的埋入氧化膜附近。

3. 发明授权

US07355207B2 Silicon carbide semiconductor device and method for manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US07355207B2
公开(公告)日：2008-04-08
申请号：US11135661
申请日：2005-05-24
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

4. 发明申请

US20060071217A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060071217A1
公开(公告)日：2006-04-06
申请号：US11206271
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura
IPC分类号： H01L31/0312
CPC分类号： H01L21/823487 , H01L29/7722
摘要： A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.
摘要翻译：半导体器件包括：垂直场效应晶体管，其具有在基板基底中的第一导电类型的衬底;形成在衬底的第一表面上的漏电极，形成在衬底的第二表面上的第一导电类型的外延层; 在半导体基底上形成的第一导电类型的源极区域，与源极区欧姆接触的源欧姆接触金属膜，从半导体基底的第二表面形成的沟槽和沿着沟槽形成的第二导电类型的栅极区域。半导体器件还包括与沟槽底部的栅极区域的引出层欧姆接触并上升到半导体基底的第二表面的栅极上升金属膜，以及连接到来自半导体基底的第二表面的栅极上升金属膜。

5. 发明授权

US06570240B1 Semiconductor device having a lateral bipolar transistor and method of manufacturing same 失效
标题翻译：具有横向双极晶体管的半导体器件及其制造方法
公开(公告)号：US06570240B1
公开(公告)日：2003-05-27
申请号：US09649616
申请日：2000-08-29
申请人： Takasumi Ohyanagi , Atsuo Watanabe
发明人： Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L2900
CPC分类号： H01L29/66265 , H01L21/84 , H01L29/7317
摘要： In order to form a semiconductor device including a lateral bipolar transistor which is a match in the device performance for a vertical bipolar transistor, an electrically conductive film which is formed by filling a trench reaching a buried oxide film in an SOI substrate with an electrically conductive film is utilized for an emitter and/or a collector, whereby a bipolar transistor is formed through a simple process.
摘要翻译：为了形成包括横向双极晶体管的半导体器件，其在垂直双极晶体管的器件性能上是匹配的，导电膜是通过在导电的SOI衬底中填充到达掩埋氧化膜的沟槽而形成的，膜用于发射极和/或集电极，由此通过简单的工艺形成双极晶体管。

6. 发明授权

US06498368B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US06498368B2
公开(公告)日：2002-12-24
申请号：US09733098
申请日：2000-12-11
申请人： Kozo Sakamoto , Yosuke Inoue , Akihiro Miyauchi , Masaki Shiraishi , Mutsuhiro Mori , Atsuo Watanabe , Takasumi Ohyanagi
发明人： Kozo Sakamoto , Yosuke Inoue , Akihiro Miyauchi , Masaki Shiraishi , Mutsuhiro Mori , Atsuo Watanabe , Takasumi Ohyanagi
IPC分类号： H01L31119
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0619 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/732 , H01L29/7397 , H01L29/7722 , H01L29/7811 , H01L29/872
摘要： In a semiconductor device having a first terminal 101 (source terminal) and a second terminal 102 (drain terminal), the substrate main surface of a semiconductor chip is on the (110) face, the main contact face of an n-type region 2 and a p-type region 4 is the {111} face perpendicular to the (110) face, elongated n-type regions 2 and elongated p-type regions 4, which are arranged alternately, form a voltage holding area. The first terminal 101 is connected to the p-type regions through wiring, and the second terminal 102 is connected to the n-type regions 2. Also, the p-type region is formed to cover the bottom comers of a gate polycrystalline silicon layer 8.
摘要翻译：在具有第一端子101（源极端子）和第二端子102（漏极端子）的半导体器件中，半导体芯片的基板主表面在（110）面上，n型区域2的主接触面并且p型区域4是垂直于（110）面的{111}面，交替布置的细长n型区域2和细长p型区域4形成电压保持区域。第一端子101通过布线连接到p型区域，并且第二端子102连接到n型区域2.而且，形成p型区域以覆盖栅极多晶硅层的底部角 8。

7. 发明授权

US07763504B2 Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US07763504B2
公开(公告)日：2010-07-27
申请号：US12071186
申请日：2008-02-19
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/338
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

8. 发明授权

US07335928B2 Semiconductor device having a metal conductor in ohmic contact with the gate region on the bottom of each the first groove 有权
标题翻译：具有与每个第一凹槽的底部上的栅极区域欧姆接触的金属导体的半导体器件
公开(公告)号：US07335928B2
公开(公告)日：2008-02-26
申请号：US11802810
申请日：2007-05-25
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Rajesh Kumar Malhan , Tsuyoshi Yamamoto , Toshiyuki Morishita
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Rajesh Kumar Malhan , Tsuyoshi Yamamoto , Toshiyuki Morishita
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/66416 , H01L29/1608 , H01L29/7722 , H01L29/8083
摘要： A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.
摘要翻译：提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极在半导体衬底的一个表面上或在沟槽槽的底部。金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。虚拟栅电极与栅极电极和外部电线电隔离。

9. 发明授权

US07230283B2 Semiconductor device having a metal conductor in ohmic contact with the gate region on the bottom of each groove 有权
标题翻译：具有与每个凹槽底部的栅极区域欧姆接触的金属导体的半导体器件
公开(公告)号：US07230283B2
公开(公告)日：2007-06-12
申请号：US11138298
申请日：2005-05-27
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Rajesh Kumar Malhan , Tsuyoshi Yamamoto , Toshiyuki Morishita
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Rajesh Kumar Malhan , Tsuyoshi Yamamoto , Toshiyuki Morishita
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/66416 , H01L29/1608 , H01L29/7722 , H01L29/8083
摘要： A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.
摘要翻译：提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极在半导体衬底的一个表面上或在沟槽槽的底部。金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。虚拟栅电极与栅极电极和外部电线电隔离。

10. 发明申请

US20050258454A1 Silicon carbide semiconductor device and method for manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US20050258454A1
公开(公告)日：2005-11-24
申请号：US11135661
申请日：2005-05-24
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/04 , H01L21/336 , H01L27/098 , H01L27/10 , H01L29/06 , H01L29/24 , H01L29/78 , H01L29/808
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

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