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1. 发明申请

US20130234087A1 NON-VOLATILE RESISTANCE CHANGE DEVICE 审中-公开
标题翻译：非易失性电阻变化器件
公开(公告)号：US20130234087A1
公开(公告)日：2013-09-12
申请号：US13605917
申请日：2012-09-06
申请人： Takashi Yamauchi , Yoshifumi Nishi , Jiezhi Chen , Akira Takashima , Minoru Amano
发明人： Takashi Yamauchi , Yoshifumi Nishi , Jiezhi Chen , Akira Takashima , Minoru Amano
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , H01L27/2463 , H01L45/1233 , H01L45/148 , H01L45/1675
摘要： A non-volatile resistance change device includes a first electrode made of a metallic element, a second electrode, a variable resistance layer formed between the first electrode and the second electrode, first wiring formed on the first electrode on a side opposite to the variable resistance layer, and second wiring formed on the second electrode on a side opposite to the variable resistance layer. If the width of the first wiring is represented as A (nm), the width of the second wiring represented as B (nm), and the distance between the first electrode and the second electrode represented as L0 (nm), the following equation is satisfied: 3 2  AB
摘要翻译：非易失性电阻变化装置包括由金属元件构成的第一电极，第二电极，形成在第一电极和第二电极之间的可变电阻层，在与可变电阻相反的一侧形成在第一电极上的第一布线层和在与可变电阻层相反的一侧形成在第二电极上的第二布线。如果将第一布线的宽度表示为A（nm），则表示为B（nm）的第二布线的宽度以及表示为L0（nm）的第一电极和第二电极之间的距离，下式为满意：3 2 AB

2. 发明申请

US20130228736A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20130228736A1
公开(公告)日：2013-09-05
申请号：US13599504
申请日：2012-08-30
申请人： Daisuke MATSUSHITA , Shosuke Fujii , Yoshifumi Nishi , Akira Takashima , Takayuki Ishikawa , Hidenori Miyagawa , Takashi Haimoto , Yusuke Arayashiki , Hideki Inokuma
发明人： Daisuke MATSUSHITA , Shosuke Fujii , Yoshifumi Nishi , Akira Takashima , Takayuki Ishikawa , Hidenori Miyagawa , Takashi Haimoto , Yusuke Arayashiki , Hideki Inokuma
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148
摘要： According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.
摘要翻译：根据一个实施例，存储器件包括第一电极，第二电极和可变电阻膜。可变电阻膜连接在第一电极和第二电极之间。第一电极包括由导电材料制成的基体中所含的金属。金属的内聚能低于导电材料的内聚能。第一电极的宽度方向的中央部的金属浓度高于第一电极的宽度方向的两端部的金属的浓度。

3. 发明授权

US08664632B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08664632B2
公开(公告)日：2014-03-04
申请号：US13599504
申请日：2012-08-30
申请人： Daisuke Matsushita , Shosuke Fujii , Yoshifumi Nishi , Akira Takashima , Takayuki Ishikawa , Hidenori Miyagawa , Takashi Haimoto , Yusuke Arayashiki , Hideki Inokuma
发明人： Daisuke Matsushita , Shosuke Fujii , Yoshifumi Nishi , Akira Takashima , Takayuki Ishikawa , Hidenori Miyagawa , Takashi Haimoto , Yusuke Arayashiki , Hideki Inokuma
IPC分类号： H01L47/00 , G11C11/00
CPC分类号： H01L45/1253 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148
摘要： According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.
摘要翻译：根据一个实施例，存储器件包括第一电极，第二电极和可变电阻膜。可变电阻膜连接在第一电极和第二电极之间。第一电极包括由导电材料制成的基体中所含的金属。金属的内聚能低于导电材料的内聚能。第一电极的宽度方向的中央部的金属浓度高于第一电极的宽度方向的两端部的金属的浓度。

4. 发明授权

US08772751B2 Variable resistance semiconductor memory device 有权
标题翻译：可变电阻半导体存储器件
公开(公告)号：US08772751B2
公开(公告)日：2014-07-08
申请号：US13234388
申请日：2011-09-16
申请人： Akira Takashima , Daisuke Matsushita , Takashi Yamauchi , Yuuichi Kamimuta , Hidenori Miyagawa
发明人： Akira Takashima , Daisuke Matsushita , Takashi Yamauchi , Yuuichi Kamimuta , Hidenori Miyagawa
IPC分类号： H01L47/00 , H01L45/00
CPC分类号： H01L45/04 , G11C11/56 , G11C13/0002 , G11C13/0007 , G11C2213/33 , G11C2213/52 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/148
摘要： According to one embodiment, a memory device includes a first electrode including a crystallized SixGe1-x layer (0≦x
摘要翻译：根据一个实施例，存储器件包括包括结晶的SixGe1-x层（0和n1E; x <1）的第一电极，包括金属元件的第二电极，在第一和第二电极之间的可变电阻部分，非晶Si层，以及控制非晶Si层中的细丝的控制电路，所述灯丝包括金属元件。

5. 发明授权

US08810043B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08810043B2
公开(公告)日：2014-08-19
申请号：US13195325
申请日：2011-08-01
申请人： Takao Nishimura , Yoshikazu Kumagaya , Akira Takashima , Kouichi Nakamura , Kazuyuki Aiba
发明人： Takao Nishimura , Yoshikazu Kumagaya , Akira Takashima , Kouichi Nakamura , Kazuyuki Aiba
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/00 , H01L23/31 , H01L21/56 , H01L23/498 , H01L25/065
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/49811 , H01L23/49833 , H01L24/13 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05684 , H01L2224/1134 , H01L2224/13027 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14 , H01L2224/1411 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/17107 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2224/81193 , H01L2224/81194 , H01L2224/81203 , H01L2224/81801 , H01L2225/06558 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19042 , H01L2924/30107 , H01L2924/351 , H01L2924/3841 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/00015 , H01L2224/05541 , H01L2224/05005
摘要： A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection member; and the connection member commonly covers the convex-shaped outside connection terminals.
摘要翻译：半导体器件包括具有设置有外部连接端子焊盘的主表面的半导体元件。半导体元件经由设置在外部连接端子焊盘上的多个凸形外部连接端子和连接构件连接到支撑板上的导电层; 并且连接构件通常覆盖凸形外部连接端子。

6. 发明授权

US08331137B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08331137B2
公开(公告)日：2012-12-11
申请号：US13234796
申请日：2011-09-16
申请人： Akira Takashima , Reika Ichihara
发明人： Akira Takashima , Reika Ichihara
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C13/0097 , G11C2013/0092 , G11C2213/33 , G11C2213/76
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell includes a variable resistance element and a capacitor connected in series between first and second conductive lines, and a control circuit applying one of first and second voltage pulses to the memory cell. The capacitor is charged by a leading edge of one of the first and second voltage pulses, and discharged a trailing edge of one of the first and second voltage pulses. The control circuit makes waveforms of the trailing edges of the first and second voltage pulses be different, changes a resistance value of the variable resistance element from a first resistance value to a second resistance value by using the first voltage pulse, and changes the resistance value of the variable resistance element from the second resistance value to the first resistance value by using the second voltage pulse.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元，其包括可变电阻元件和串联连接在第一和第二导线之间的电容器，以及将第一和第二电压脉冲之一施加到存储单元的控制电路。电容器由第一和第二电压脉冲之一的前沿充电，并且将第一和第二电压脉冲之一的后沿放电。控制电路使得第一和第二电压脉冲的后沿的波形不同，通过使用第一电压脉冲将可变电阻元件的电阻值从第一电阻值改变为第二电阻值，并且改变电阻值通过使用第二电压脉冲从第二电阻值到第一电阻值。

7. 发明申请

US20120025294A1 SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120025294A1
公开(公告)日：2012-02-02
申请号：US13208454
申请日：2011-08-12
申请人： Masao SHINGU , Akira Takashima , Koichi Muraoka
发明人： Masao SHINGU , Akira Takashima , Koichi Muraoka
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/788 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/513 , H01L29/66825
摘要： There is provided a semiconductor device in which degradation of reliability originating in the interface between an upper insulating layer and an element isolation insulating layer is suppressed. The semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO2, SiN, and SiON, the upper insulating layer is an oxide containing at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si, and respective lengths Lcharge, Ltop, and Lgate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “Lcharge
摘要翻译：提供一种半导体器件，其中抑制源于上绝缘层和元件隔离绝缘层之间的界面的可靠性的劣化。半导体器件包括：半导体区域; 多个堆叠结构，其各自设置在所述半导体区域上，并且具有依次堆叠的隧道绝缘膜，电荷存储层，上绝缘层和控制电极; 设置在所述多个堆叠结构的侧面上的元件隔离绝缘层; 以及设置在半导体区域和多个堆叠结构中的源极 - 漏极区域。元件隔离绝缘层包括SiO 2，SiN和SiON中的至少一种，上绝缘层是含有选自稀土金属，Y，Zr和Hf中的至少一种金属M的氧化物，Si ，并且沟道长度方向上的电荷存储层，上绝缘层和控制电极的各自的长度Lcharge，Ltop和Lgate满足关系“Lcharge

8. 发明授权

US07986016B2 Semiconductor device and associated manufacturing methodology for decreasing thermal instability between an insulating layer and a substrate 有权
标题翻译：半导体器件和相关的制造方法，用于降低绝缘层和衬底之间的热不稳定性
公开(公告)号：US07986016B2
公开(公告)日：2011-07-26
申请号：US12482054
申请日：2009-06-10
申请人： Yoshiki Kamata , Akira Takashima
发明人： Yoshiki Kamata , Akira Takashima
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L29/24 , H01L21/02381 , H01L21/02521 , H01L21/02532 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/1054 , H01L29/517 , H01L29/785
摘要： According to an aspect of the present invention, there is provided a semiconductor device including: a substrate that includes a semiconductor region including Ge as a primary component; a compound layer that is formed above the semiconductor region, that includes Ge and that has a non-metallic characteristic; an insulator film that is formed above the compound layer; an electrode that is formed above the insulator film; and source/drain regions that is formed in the substrate so as to sandwich the electrode therebetween.
摘要翻译：根据本发明的一个方面，提供了一种半导体器件，包括：衬底，其包括以Ge为主要成分的半导体区域; 形成在半导体区域上方的包含Ge并且具有非金属特性的化合物层; 形成在化合物层上方的绝缘膜; 形成在绝缘膜上的电极; 以及形成在基板中以将电极夹在其间的源极/漏极区域。

9. 发明授权

US07884459B2 Semiconductor device suitable for a stacked structure 有权
标题翻译：适用于堆叠结构的半导体器件
公开(公告)号：US07884459B2
公开(公告)日：2011-02-08
申请号：US12210645
申请日：2008-09-15
申请人： Eiji Yoshida , Takao Ohno , Yoshito Akutagawa , Koji Sawahata , Masataka Mizukoshi , Takao Nishimura , Akira Takashima , Mitsuhisa Watanabe
发明人： Eiji Yoshida , Takao Ohno , Yoshito Akutagawa , Koji Sawahata , Masataka Mizukoshi , Takao Nishimura , Akira Takashima , Mitsuhisa Watanabe
IPC分类号： H01L23/02
CPC分类号： H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/02371 , H01L2224/0401 , H01L2224/05572 , H01L2224/06181 , H01L2224/13008 , H01L2224/13009 , H01L2224/13025 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/45144 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/0106 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
摘要翻译：提供一种半导体器件，其形成具有彼此堆叠的半导体器件的三维半导体器件。在该半导体器件中，在具有形成在外侧的主面上的集成电路单元和电极焊盘的硅半导体基板中形成有孔。通过蚀刻形成孔，电极焊盘用作蚀刻停止层。埋入电极形成在孔中。该嵌入电极用于将电极焊盘导电到硅半导体衬底的底侧的主表面。

10. 发明授权

US07863695B2 Complementary MISFET semiconductor device having an atomic density ratio aluminum/lanthanum (Al/La) in the gate insulating layer of PMIS is larger than that of the NMIS 有权
标题翻译：在PMIS的栅极绝缘层中具有铝/镧原子密度比（Al / La）的互补MISFET半导体器件大于NMIS
公开(公告)号：US07863695B2
公开(公告)日：2011-01-04
申请号：US12200599
申请日：2008-08-28
申请人： Masamichi Suzuki , Masato Koyama , Yoshinori Tsuchiya , Hirotaka Nishino , Reika Ichihara , Akira Takashima
发明人： Masamichi Suzuki , Masato Koyama , Yoshinori Tsuchiya , Hirotaka Nishino , Reika Ichihara , Akira Takashima
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/26506 , H01L21/31155 , H01L21/823842 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/7842 , H01L29/7846 , H01L29/785
摘要： A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film.
摘要翻译：互补半导体器件包括半导体衬底，形成在半导体衬底的表面上的第一半导体区域，形成在半导体衬底的离开第一半导体区域的表面上的第二半导体区域，具有第一栅极的n-MIS晶体管形成在第一半导体区域上的包括La和Al的绝缘膜和形成在栅极绝缘膜上的第一栅电极和形成在第二半导体区上的具有包括La和Al的第二栅极绝缘膜的p-MIS晶体管，以及形成在所述栅极绝缘膜上的第二栅电极，所述第二栅极绝缘膜中的原子密度比Al / La大于所述第一栅极绝缘膜中的原子密度比Al / La。

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