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    • 1. 发明授权
    • Processing unit
    • 处理单元
    • US08001362B2
    • 2011-08-16
    • US12633108
    • 2009-12-08
    • Atsushi FusejimaTakashi SuzukiToshio YoshidaYasunobu Akizuki
    • Atsushi FusejimaTakashi SuzukiToshio YoshidaYasunobu Akizuki
    • G06F9/38G06F9/46
    • G06F9/3851G06F9/3013G06F9/3857G06F11/3466G06F2201/88
    • A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of instructions, a commit scope register for storing instructions of completion candidates stored in each commit stack entry unit by execution by each thread execution unit and performing processing for completion of instructions included in the thread, and a thread selecting means for sending commit events of the instructions to a performance analysis circuit provided in each thread execution unit corresponding to the instructions when performing commit processing for instructions stored in the commit scope register.
    • 处理单元包括多个线程执行单元,每个线程执行单元具有用于测量执行指令的各种类型的事件的性能分析电路和用于控制执行指令完成的提交堆栈输入单元,并且每个线程执行单元执行具有多个 指令,用于通过每个线程执行单元的执行来存储存储在每个提交栈输入单元中的完成候选的指令的提交范围寄存器,并且执行用于完成包括在该线程中的指令的处理;线程选择装置,用于发送指令的提交事件 涉及在对存储在提交范围寄存器中的指令执行提交处理时对应于指令的每个线程执行单元中提供的性能分析电路。
    • 2. 发明授权
    • Inter-thread load arbitration control detecting information registered in commit stack entry units and controlling instruction input control unit
    • 在提交堆栈输入单元中登记的线程间负载仲裁控制检测信息和控制指令输入控制单元
    • US08561079B2
    • 2013-10-15
    • US12635801
    • 2009-12-11
    • Takashi SuzukiToshio Yoshida
    • Takashi SuzukiToshio Yoshida
    • G06F9/46G06F15/00
    • G06F9/3851
    • The information processing device in the simultaneous multi-threading system is operated in an inter-thread performance load arbitration control method, and includes: an instruction input control unit for sharing among threads control of inputting an instruction in an arithmetic unit for acquiring the instruction from memory and performing an operation on the basis of the instruction; a commit stack entry provided for each thread for holding information obtained by decoding the instruction; an instruction completion order control unit for updating the memory and a general purpose register depending on an arithmetic result obtained by the arithmetic unit in an order of the instructions input from the instruction input control unit; and a performance load balance analysis unit for detecting the information registered in the commit stack entry and controlling the instruction input control unit.
    • 同时多线程系统中的信息处理装置以线程间性能负载仲裁控制方式进行操作,包括:指令输入控制单元,用于在线程之间共享输入用于获取指令的算术单元中的指令的控制 存储器并基于该指令执行操作; 为每个线程提供的用于保存通过解码指令而获得的信息的提交栈条目; 指令完成顺序控制单元,用于根据从指令输入控制单元输入的指令的顺序,根据运算单元获得的运算结果来更新存储器和通用寄存器; 以及性能负载平衡分析单元,用于检测在提交堆栈条目中登记的信息并控制指令输入控制单元。
    • 3. 发明授权
    • Information processing apparatus and method of controlling register
    • 信息处理装置和控制寄存器的方法
    • US08019973B2
    • 2011-09-13
    • US12638764
    • 2009-12-15
    • Takashi SuzukiToshio Yoshida
    • Takashi SuzukiToshio Yoshida
    • G06F9/312G06F9/52
    • G06F9/3885G06F9/30127G06F9/3824G06F9/3851
    • An information processing apparatus and a method of controlling the same that employs a register window system and a Simultaneous Multithreading method for reducing circuit areas by sharing a data transfer bus between threads, said bus connecting a master register and a work register provided for each thread and for avoiding interference in instruction execution with other threads caused by a conflict between accesses to a register between threads. An information processing apparatus and a method of controlling the information processing apparatus employing a register window system for register reading, in which a master register and a work register are held for each thread and a bus for transferring data from the master to the work register is shared by threads in order to realize Simultaneous Multithreading.
    • 一种信息处理装置及其控制方法,其采用寄存器窗口系统和同时多线程方法,用于通过在线程之间共享数据传输总线来减少电路面积,所述总线连接主寄存器和为每个线程提供的工作寄存器, 用于避免在对线程之间的寄存器的访问之间的冲突引起的与其他线程的指令执行的干扰。 一种信息处理设备和方法,用于控制信息处理设备,该信息处理设备采用用于寄存器读取的寄存器窗口系统,其中为每个线程保持主寄存器和工作寄存器,并且用于将数据从主器件传送到工作寄存器的总线是 由线程共享,以实现同时多线程。
    • 4. 发明申请
    • PROCESSING UNIT
    • 处理单元
    • US20100088491A1
    • 2010-04-08
    • US12633108
    • 2009-12-08
    • Atsushi FUSEJIMATakashi SuzukiToshio YoshidaYasunobu Akizuki
    • Atsushi FUSEJIMATakashi SuzukiToshio YoshidaYasunobu Akizuki
    • G06F9/46G06F9/30
    • G06F9/3851G06F9/3013G06F9/3857G06F11/3466G06F2201/88
    • A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of instructions, a commit scope register for storing instructions of completion candidates stored in each commit stack entry unit by execution by each thread execution unit and performing processing for completion of instructions included in the thread, and a thread selecting means for sending commit events of the instructions to a performance analysis circuit provided in each thread execution unit corresponding to the instructions when performing commit processing for instructions stored in the commit scope register.
    • 处理单元包括多个线程执行单元,每个线程执行单元具有用于测量执行指令的各种类型的事件的性能分析电路和用于控制执行指令完成的提交堆栈输入单元,并且每个线程执行单元执行具有多个 指令,用于通过每个线程执行单元的执行来存储存储在每个提交栈输入单元中的完成候选的指令的提交范围寄存器,并且执行用于完成包括在该线程中的指令的处理;线程选择装置,用于发送指令的提交事件 涉及在对存储在提交范围寄存器中的指令执行提交处理时对应于指令的每个线程执行单元中提供的性能分析电路。