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1. 再颁专利

USRE41879E1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：USRE41879E1
公开(公告)日：2010-10-26
申请号：US12155392
申请日：2008-06-03
申请人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
发明人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
IPC分类号： G11C16/06
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1063 , G11C2207/229
摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.
摘要翻译：提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

2. 发明授权

US07136313B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07136313B2
公开(公告)日：2006-11-14
申请号：US11121939
申请日：2005-05-05
申请人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
发明人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/816 , G11C11/22 , G11C29/789 , G11C2029/4402
摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost.A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.
摘要翻译：为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

3. 发明申请

US20050265090A1 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US20050265090A1
公开(公告)日：2005-12-01
申请号：US11121939
申请日：2005-05-05
申请人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
发明人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C11/22 , G11C7/00 , G11C29/00 , G11C29/12
CPC分类号： G11C29/816 , G11C11/22 , G11C29/789 , G11C2029/4402
摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.
摘要翻译：为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

4. 发明授权

US07307866B2 Ferroelectric memory and method for reading data from the ferroelectric memory 有权
标题翻译：铁电存储器和从铁电存储器读取数据的方法
公开(公告)号：US07307866B2
公开(公告)日：2007-12-11
申请号：US11132196
申请日：2005-05-19
申请人： Kunisato Yamaoka , Hiroshige Hirano , Yasushi Gohou , Shunichi Iwanari , Yasuo Murakuki , Masahiko Sakagami , Tetsuji Nakakuma , Takashi Miki
发明人： Kunisato Yamaoka , Hiroshige Hirano , Yasushi Gohou , Shunichi Iwanari , Yasuo Murakuki , Masahiko Sakagami , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C11/22 , G11C11/42 , G11C5/14 , G11C7/00 , G11C7/02
CPC分类号： G11C11/22
摘要： A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.
摘要翻译：本发明的铁电存储器包括：多个正常单元，每个单元包括用于保持数据的第一铁电电容器和连接到第一铁电电容器的第一电极的第一晶体管; 连接到第一晶体管的第一位线; 第一位线预充电电路，其是设置在第一位线和地之间的开关电路; 以及连接到第一晶体管的栅极的字线。在驱动第一位线预充电电路以放电第一位线的电位之前，字线被去激活以将第一铁电电容器与第一位线断开。

5. 发明授权

US07280406B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07280406B2
公开(公告)日：2007-10-09
申请号：US11344199
申请日：2006-02-01
申请人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
发明人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
IPC分类号： G11C16/06
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1063 , G11C2207/229
摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.
摘要翻译：提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

6. 发明申请

US20060171246A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060171246A1
公开(公告)日：2006-08-03
申请号：US11344199
申请日：2006-02-01
申请人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
发明人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1063 , G11C2207/229
摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.
摘要翻译：提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

7. 发明申请

US20060113581A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20060113581A1
公开(公告)日：2006-06-01
申请号：US11289441
申请日：2005-11-30
申请人： Takashi Miki , Hiroshige Hirano
发明人： Takashi Miki , Hiroshige Hirano
IPC分类号： H01L29/94
CPC分类号： H01L27/11502 , H01L23/564 , H01L27/11507 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device having a memory cell array in which plural memory transistors and plural memory call capacitors, which are components of memory cells, are arranged, comprises a first wiring layer formed on the memory cell array, and a second wiring layer formed above the first wiring layer, wherein a wiring density of the first wiring layer on the memory cell array is higher than a wiring density of the second wiring layer on the memory cell array. Therefore, a hydrogen barrier property for the capacitors is improved, and an adverse effect due to stress applied to the capacitors is reduced, thereby suppressing deterioration of capacitor characteristics.
摘要翻译：一种具有存储单元阵列的半导体存储器件，其中布置有作为存储单元的组件的多个存储晶体管和多个存储器调用电容器，包括形成在存储单元阵列上的第一布线层和形成在存储单元阵列上方的第二布线层第一布线层，其中存储单元阵列上的第一布线层的布线密度高于存储单元阵列上的第二布线层的布线密度。因此，电容器的氢阻挡性提高，并且由于施加到电容器的应力引起的不利影响降低，从而抑制电容器特性的劣化。

8. 发明申请

US20050259461A1 Ferroelectric memory and method for reading data from the ferroelectric memory 有权
标题翻译：铁电存储器和从铁电存储器读取数据的方法
公开(公告)号：US20050259461A1
公开(公告)日：2005-11-24
申请号：US11132196
申请日：2005-05-19
申请人： Kunisato Yamaoka , Hiroshige Hirano , Yasushi Gohou , Shunichi Iwanari , Yasuo Murakuki , Masahiko Sakagami , Tetsuji Nakakuma , Takashi Miki
发明人： Kunisato Yamaoka , Hiroshige Hirano , Yasushi Gohou , Shunichi Iwanari , Yasuo Murakuki , Masahiko Sakagami , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C11/22 , H01L27/10
CPC分类号： G11C11/22
摘要： A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.
摘要翻译：本发明的铁电存储器包括：多个正常单元，每个单元包括用于保持数据的第一铁电电容器和连接到第一铁电电容器的第一电极的第一晶体管; 连接到第一晶体管的第一位线; 第一位线预充电电路，其是设置在第一位线和地之间的开关电路; 以及连接到第一晶体管的栅极的字线。在驱动第一位线预充电电路以放电第一位线的电位之前，字线被去激活以将第一铁电电容器与第一位线断开。

9. 发明授权

US08785651B2 Method for manufacturing a boronic acid ester compound 失效
标题翻译：硼酸酯化合物的制造方法
公开(公告)号：US08785651B2
公开(公告)日：2014-07-22
申请号：US13142536
申请日：2009-03-24
申请人： Takashi Miki , Yasuharu Shimasaki , Srinivasan Babu , Zhigang Cheng , Mark E. Reynolds , Qingping Tian
发明人： Takashi Miki , Yasuharu Shimasaki , Srinivasan Babu , Zhigang Cheng , Mark E. Reynolds , Qingping Tian
IPC分类号： C07F5/04 , C07F5/02
CPC分类号： C07F5/025
摘要： The present invention relates to a method for manufacturing a boronic acid ester compound, characterized by reacting an aryl halide compound and a diboron ester compound in the presence of a nitrogen-containing organic base, a nickel catalyst, a phosphine compound and a solvent. According to the manufacturing method of the present invention, even if a nickel catalyst is used as the catalyst, a desired boronic acid ester compound can be obtained in a sufficiently high yield. Furthermore, even if aryl chloride or aryl bromide having relatively low price and low reactivity, was used as the aryl halide compound, a desired boronic acid ester compound can be obtained in a sufficiently high yield.
摘要翻译：硼酸酯化合物的制造方法技术领域本发明涉及硼酸酯化合物的制造方法，其特征在于，在含氮有机碱，镍催化剂，膦化合物和溶剂的存在下，使芳基卤化合物与二硼酸酯化合物反应。根据本发明的制造方法，即使使用镍催化剂作为催化剂，也能以足够高的收率获得所需的硼酸酯化合物。此外，即使使用价格低廉，反应性低的芳基氯或芳基溴作为芳基卤化合物，可以以足够高的收率得到所需的硼酸酯化合物。

10. 发明申请

US20130334041A1 DEVICE FOR MEASURING BIOLOGICAL SAMPLE 有权
标题翻译：用于测量生物样品的装置
公开(公告)号：US20130334041A1
公开(公告)日：2013-12-19
申请号：US14001954
申请日：2012-03-28
申请人： Reiko Kondo , Takashi Miki , Atsushi Watanabe
发明人： Reiko Kondo , Takashi Miki , Atsushi Watanabe
IPC分类号： G01N27/327
CPC分类号： G01N27/327 , A61B5/14532 , A61B5/150022 , A61B5/150358 , A61B5/15126 , A61B5/157 , C12Q1/006 , C12Q1/54 , G01N33/4875 , G01N33/64 , G01N33/66 , G01N2333/904
摘要： The objective of the invention is to enhance measurement accuracy in a device for measuring a biological sample. To attain this objective, the invention is provided with a main case (2) having a sensor insertion section (1), a measurement section (7) connected to the sensor insertion section (1), a controller (8) connected to the measurement section (7), and a display (3) connected to the controller (8). An acceleration sensor (5) is furnished for detecting a shock applied to the sensor insertion section (1).
摘要翻译：本发明的目的是提高用于测量生物样品的装置中的测量精度。为了达到这个目的，本发明提供了一种具有传感器插入部分（1）的主壳体（2），连接到传感器插入部分（1）的测量部分（7），连接到测量装置部分（7）和连接到控制器（8）的显示器（3）。提供加速度传感器（5），用于检测施加到传感器插入部分（1）的冲击。

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