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1. 再颁专利

USRE41879E1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：USRE41879E1
公开(公告)日：2010-10-26
申请号：US12155392
申请日：2008-06-03
申请人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
发明人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
IPC分类号： G11C16/06
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1063 , G11C2207/229
摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.
摘要翻译：提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

2. 发明授权

US07136313B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07136313B2
公开(公告)日：2006-11-14
申请号：US11121939
申请日：2005-05-05
申请人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
发明人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/816 , G11C11/22 , G11C29/789 , G11C2029/4402
摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost.A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.
摘要翻译：为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

3. 发明申请

US20050265090A1 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US20050265090A1
公开(公告)日：2005-12-01
申请号：US11121939
申请日：2005-05-05
申请人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
发明人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C11/22 , G11C7/00 , G11C29/00 , G11C29/12
CPC分类号： G11C29/816 , G11C11/22 , G11C29/789 , G11C2029/4402
摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.
摘要翻译：为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

4. 发明授权

US07307866B2 Ferroelectric memory and method for reading data from the ferroelectric memory 有权
标题翻译：铁电存储器和从铁电存储器读取数据的方法
公开(公告)号：US07307866B2
公开(公告)日：2007-12-11
申请号：US11132196
申请日：2005-05-19
申请人： Kunisato Yamaoka , Hiroshige Hirano , Yasushi Gohou , Shunichi Iwanari , Yasuo Murakuki , Masahiko Sakagami , Tetsuji Nakakuma , Takashi Miki
发明人： Kunisato Yamaoka , Hiroshige Hirano , Yasushi Gohou , Shunichi Iwanari , Yasuo Murakuki , Masahiko Sakagami , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C11/22 , G11C11/42 , G11C5/14 , G11C7/00 , G11C7/02
CPC分类号： G11C11/22
摘要： A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.
摘要翻译：本发明的铁电存储器包括：多个正常单元，每个单元包括用于保持数据的第一铁电电容器和连接到第一铁电电容器的第一电极的第一晶体管; 连接到第一晶体管的第一位线; 第一位线预充电电路，其是设置在第一位线和地之间的开关电路; 以及连接到第一晶体管的栅极的字线。在驱动第一位线预充电电路以放电第一位线的电位之前，字线被去激活以将第一铁电电容器与第一位线断开。

5. 发明授权

US07280406B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07280406B2
公开(公告)日：2007-10-09
申请号：US11344199
申请日：2006-02-01
申请人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
发明人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
IPC分类号： G11C16/06
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1063 , G11C2207/229
摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.
摘要翻译：提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

6. 发明申请

US20060171246A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060171246A1
公开(公告)日：2006-08-03
申请号：US11344199
申请日：2006-02-01
申请人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
发明人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1063 , G11C2207/229
摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.
摘要翻译：提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

7. 发明申请

US20050259461A1 Ferroelectric memory and method for reading data from the ferroelectric memory 有权
标题翻译：铁电存储器和从铁电存储器读取数据的方法
公开(公告)号：US20050259461A1
公开(公告)日：2005-11-24
申请号：US11132196
申请日：2005-05-19
申请人： Kunisato Yamaoka , Hiroshige Hirano , Yasushi Gohou , Shunichi Iwanari , Yasuo Murakuki , Masahiko Sakagami , Tetsuji Nakakuma , Takashi Miki
发明人： Kunisato Yamaoka , Hiroshige Hirano , Yasushi Gohou , Shunichi Iwanari , Yasuo Murakuki , Masahiko Sakagami , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C11/22 , H01L27/10
CPC分类号： G11C11/22
摘要： A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.
摘要翻译：本发明的铁电存储器包括：多个正常单元，每个单元包括用于保持数据的第一铁电电容器和连接到第一铁电电容器的第一电极的第一晶体管; 连接到第一晶体管的第一位线; 第一位线预充电电路，其是设置在第一位线和地之间的开关电路; 以及连接到第一晶体管的栅极的字线。在驱动第一位线预充电电路以放电第一位线的电位之前，字线被去激活以将第一铁电电容器与第一位线断开。

8. 发明授权

US07835169B2 Semiconductor memory device and semiconductor memory system 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US07835169B2
公开(公告)日：2010-11-16
申请号：US12368622
申请日：2009-02-10
申请人： Yasuo Murakuki , Yasushi Gohou , Shunichi Iwanari , Masanori Matsuura , Yoshiaki Nakao
发明人： Yasuo Murakuki , Yasushi Gohou , Shunichi Iwanari , Masanori Matsuura , Yoshiaki Nakao
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines.
摘要翻译：半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括以矩阵图案排列的多个存储单元，以及多个存储单元阵列共享的单元板板线，每个单元板线对应于存储单元的行和每个单元格板线连接到相应行之一的存储单元。每个存储单元阵列包括多个字线，每个字线对应于存储单元阵列中存储单元的行中的每一行。连接到每个单元格板行的存储单元的数量大于连接到与每个单元格板行相对应的一个字线的存储单元的数量。

9. 发明申请

US20100023840A1 ECC CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM 审中-公开
标题翻译： ECC电路，半导体存储器件，存储器系统
公开(公告)号：US20100023840A1
公开(公告)日：2010-01-28
申请号：US12480294
申请日：2009-06-08
申请人： Yoshiaki Nakao , Yasushi Gohou , Shunichi Iwanari , Masanori Matsuura , Yasuo Murakuki
发明人： Yoshiaki Nakao , Yasushi Gohou , Shunichi Iwanari , Masanori Matsuura , Yasuo Murakuki
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/13 , G06F11/1008 , H03M13/19
摘要： A syndrome generation section generates a syndrome from input data having d bits of data bits and k bits of parity bits. A syndrome table stores a syndrome pattern indicating that no error has occurred in the input data and syndrome patterns indicating an error position. A comparison section compares the syndrome generated by the syndrome generation section with the syndrome patterns in the syndrome table, outputs a match signal when a syndrome pattern matching the syndrome exists, and outputs a no-match signal when no syndrome pattern matching the syndrome exists. An error correction section corrects the error in the input data based on the match signal from the comparison section.
摘要翻译：校正子产生部分从具有数据位d位和奇偶校验位k位的输入数据生成校正子。校正子表存储指示在输入数据中没有发生错误的校正子模式和指示错误位置的校正子模式。比较部分将由校正子产生部分产生的综合征与综合征表中的综合征模式进行比较，当不存在匹配该综合征的综合征模式时，输出匹配信号，并且当不存在与该综合征相匹配的症状模式时，输出不匹配信号。误差校正部分根据比较部分的匹配信号校正输入数据中的误差。

10. 发明授权

US06912149B2 Ferroelectric memory device and method for reading data from the same 有权
标题翻译：铁电存储器件和从其读取数据的方法
公开(公告)号：US06912149B2
公开(公告)日：2005-06-28
申请号：US10620614
申请日：2003-07-17
申请人： Kunisato Yamaoka , Hiroshige Hirano , Yasuo Murakuki
发明人： Kunisato Yamaoka , Hiroshige Hirano , Yasuo Murakuki
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a plurality of bit line pairs, a plurality of sense amplifiers, a plurality of memory cells, a plurality of reference cells, and a control circuit. Each of the bit line pairs is composed of first and second bit lines. Each of the sense amplifiers amplifies a potential difference across the corresponding bit line pair. The memory cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. The reference cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. In addition, each of the reference cells on each of the bit line pairs retains data different from data of a reference cell on the adjacent bit line pair. The control circuit drives the sense amplifiers, the memory cells, and the reference cells. During the drive of the sense amplifier, the control circuit inactivates a reference word line connected to the reference cell.
摘要翻译：铁电存储器件包括多个位线对，多个读出放大器，多个存储单元，多个参考单元和控制电路。每个位线对由第一和第二位线组成。每个读出放大器放大对应位线对上的电位差。为每个位线对提供存储单元，并且每个由晶体管和铁电电容器构成。为每个位线对提供参考单元，每个由晶体管和铁电电容器组成。此外，每个位线对上的每个参考单元保留与相邻位线对上的参考单元的数据不同的数据。控制电路驱动读出放大器，存储单元和参考单元。在读出放大器的驱动期间，控制电路使连接到参考单元的参考字线失活。

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