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1. 发明授权

US08354706B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08354706B2
公开(公告)日：2013-01-15
申请号：US12719193
申请日：2010-03-08
申请人： Takahisa Kanemura , Tomomi Kusaka , Takashi Izumida , Masaki Kondo , Nobutoshi Aoki
发明人： Takahisa Kanemura , Tomomi Kusaka , Takashi Izumida , Masaki Kondo , Nobutoshi Aoki
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , G11C16/0441 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/42324
摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer.
摘要翻译：根据本发明实施例的半导体存储器件包括衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的第一栅极绝缘体，形成在第一栅绝缘体上的第一浮栅，第二栅绝缘体形成在第一浮栅上并用作FN隧穿膜的栅极绝缘体，形成在第二栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的栅极绝缘体，以及形成在栅极绝缘体上的控制栅极所述隔间绝缘体，所述第一和第二浮动栅极中的至少一个包括金属层。

2. 发明申请

US20100295112A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20100295112A1
公开(公告)日：2010-11-25
申请号：US12721757
申请日：2010-03-11
申请人： Takashi Izumida , Nobutoshi Aoki , Masaki Kondo , Takahisa Kanemura
发明人： Takashi Izumida , Nobutoshi Aoki , Masaki Kondo , Takahisa Kanemura
IPC分类号： H01L27/115
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.
摘要翻译：半导体存储装置具有半导体基板，在半导体基板上形成有规定间隔的多个第一绝缘膜，在第一方向上形成在第一绝缘膜之间的元件隔离区域，包括第一电荷累积膜的浮栅电极形成在所述第一绝缘膜上的第二电荷累积膜，形成在所述第一电荷累积膜上并且具有与所述第一方向正交的第二方向的宽度小于所述第一电荷累积膜的宽度的第二电荷累积膜，以及形成的第三电荷累积膜在第二电荷累积膜上并且具有大于第二电荷累积膜的宽度的第二方向的宽度，形成在第二电荷累积膜上以及在第二电荷累积膜和元件隔离区之间的第二绝缘膜，形成在电荷累积膜上的第三绝缘膜和沿着第二方向的元件隔离区域，以及形成在第三绝缘膜上的控制栅极电极。

3. 发明授权

US08212306B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US08212306B2
公开(公告)日：2012-07-03
申请号：US12721757
申请日：2010-03-11
申请人： Takashi Izumida , Nobutoshi Aoki , Masaki Kondo , Takahisa Kanemura
发明人： Takashi Izumida , Nobutoshi Aoki , Masaki Kondo , Takahisa Kanemura
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.
摘要翻译：半导体存储装置具有半导体基板，在半导体基板上形成有规定间隔的多个第一绝缘膜，在第一方向上形成在第一绝缘膜之间的元件隔离区域，包括第一电荷累积膜的浮栅电极形成在所述第一绝缘膜上的第二电荷累积膜，形成在所述第一电荷累积膜上并且具有与所述第一方向正交的第二方向的宽度小于所述第一电荷累积膜的宽度的第二电荷累积膜，以及形成的第三电荷累积膜在第二电荷累积膜上并且具有大于第二电荷累积膜的宽度的第二方向的宽度，形成在第二电荷累积膜上以及在第二电荷累积膜和元件隔离区之间的第二绝缘膜，形成在电荷累积膜上的第三绝缘膜和沿着第二方向的元件隔离区域，以及形成在第三绝缘膜上的控制栅极电极。

4. 发明授权

US07842998B2 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07842998B2
公开(公告)日：2010-11-30
申请号：US12248449
申请日：2008-10-09
申请人： Takahisa Kanemura , Takashi Izumida , Nobutoshi Aoki
发明人： Takahisa Kanemura , Takashi Izumida , Nobutoshi Aoki
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a semiconductor substrate; memory cell transistors that are series-connected; and a select transistor that includes: a first diffusion region that is formed in the semiconductor substrate at one end of the memory cell transistors; a first insulating film that is formed on the semiconductor substrate at a side of the first diffusion region; a select gate electrode that is formed on the first insulating film; a semiconductor pillar that is formed to extend upward from the semiconductor substrate and to be separated from the select gate electrode; a second insulating film that is formed between the select gate electrode and the semiconductor pillar; and a second diffusion region that is formed on the semiconductor pillar.
摘要翻译：根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括：半导体衬底; 串联连接的存储单元晶体管; 以及选择晶体管，其包括：在所述存储单元晶体管的一端形成在所述半导体衬底中的第一扩散区域; 在所述第一扩散区域的一侧形成在所述半导体基板上的第一绝缘膜; 形成在所述第一绝缘膜上的选择栅电极; 形成为从半导体衬底向上延伸并与选择栅电极分离的半导体柱; 形成在选择栅电极和半导体柱之间的第二绝缘膜; 以及形成在所述半导体柱上的第二扩散区域。

5. 发明授权

US08258562B2 Semiconductor device having tri-gate structure and manufacturing method thereof 有权
标题翻译：具有三栅结构的半导体器件及其制造方法
公开(公告)号：US08258562B2
公开(公告)日：2012-09-04
申请号：US12470030
申请日：2009-05-21
申请人： Takashi Izumida , Takahisa Kanemura , Nobutoshi Aoki
发明人： Takashi Izumida , Takahisa Kanemura , Nobutoshi Aoki
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.
摘要翻译：本发明实施例的半导体器件包括为存储单元提供的存储单元和选择栅极晶体管。选择栅极晶体管的栅电极具有三栅结构，其中形成在选择栅极晶体管的沟道上方的栅极绝缘膜的上表面被设定为高于栅极绝缘膜的元件隔离区的上表面的一部分选择栅极晶体管。

6. 发明申请

US20090289293A1 SEMICONDUCTOR DEVICE HAVING TRI-GATE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有三门结构的半导体器件及其制造方法
公开(公告)号：US20090289293A1
公开(公告)日：2009-11-26
申请号：US12470030
申请日：2009-05-21
申请人： Takashi IZUMIDA , Takahisa Kanemura , Nobutoshi Aoki
发明人： Takashi IZUMIDA , Takahisa Kanemura , Nobutoshi Aoki
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.
摘要翻译：本发明实施例的半导体器件包括为存储单元提供的存储单元和选择栅极晶体管。选择栅极晶体管的栅电极具有三栅结构，其中形成在选择栅极晶体管的沟道上方的栅极绝缘膜的上表面被设定为高于栅极绝缘膜的元件隔离区的上表面的一部分选择栅极晶体管。

7. 发明授权

US06516237B1 System for and method of preparing manufacturing process specifications and production control system 失效
标题翻译：制造工艺规范和生产控制系统的制备方法和制备方法
公开(公告)号：US06516237B1
公开(公告)日：2003-02-04
申请号：US09086935
申请日：1998-05-29
申请人： Nobutoshi Aoki , Takahisa Kanemura
发明人： Nobutoshi Aoki , Takahisa Kanemura
IPC分类号： G06F1900
CPC分类号： G05B19/41885 , G05B17/02 , G05B2219/32343 , G05B2219/32366 , G05B2219/32385 , G05B2219/45031 , Y02P90/26
摘要： A system for preparing manufacturing-process specifications employs process data serving both for a production control system and a simulation system, and effectively uses a result of simulation. The system prepares the manufacturing-process specifications through the steps of controlling apparatuses according to the manufacturing-process specifications, to carry out manufacturing processes; collecting data measured through the manufacturing processes; simulating the manufacturing processes according to corresponding models and parameters; correcting the models and parameters according to the collected data; and amending the manufacturing-process specifications according to a result of the simulation.
摘要翻译：用于制备制造工艺规范的系统采用用于生产控制系统和仿真系统的过程数据，并且有效地使用模拟结果。该系统通过根据制造工艺规范控制装置的步骤来制备制造工艺规范，以进行制造工艺; 收集通过制造过程测量的数据; 根据相应的模型和参数模拟制造过程; 根据收集的数据校正模型和参数; 并根据模拟结果修改制造过程规范。

8. 发明授权

US08148217B2 Semiconductor manufacturing method and semiconductor device 有权
标题翻译：半导体制造方法和半导体器件
公开(公告)号：US08148217B2
公开(公告)日：2012-04-03
申请号：US13099587
申请日：2011-05-03
申请人： Takashi Izumida , Sanae Ito , Takahisa Kanemura
发明人： Takashi Izumida , Sanae Ito , Takahisa Kanemura
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78609
摘要： A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
摘要翻译：制造半导体器件的方法包括在第一导电型半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成突出半导体层，在半导体衬底上形成第一绝缘层为了覆盖突出半导体层的下部，将第一导电型杂质掺杂到第一绝缘层中，从而在突出半导体层的下部形成高杂质浓度层，在侧面形成栅极绝缘膜所述突出半导体层的表面从所述第一绝缘层的上表面向上延伸，并且在所述栅极绝缘膜上和所述第一绝缘膜上形成栅电极。

9. 发明申请

US20110207309A1 SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE 有权
标题翻译：半导体制造方法和半导体器件
公开(公告)号：US20110207309A1
公开(公告)日：2011-08-25
申请号：US13099587
申请日：2011-05-03
申请人： Takashi IZUMIDA , Sanae Ito , Takahisa Kanemura
发明人： Takashi IZUMIDA , Sanae Ito , Takahisa Kanemura
IPC分类号： H01L21/28
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78609
摘要： A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
摘要翻译：制造半导体器件的方法包括在第一导电型半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成突出半导体层，在半导体衬底上形成第一绝缘层为了覆盖突出半导体层的下部，将第一导电型杂质掺杂到第一绝缘层中，从而在突出半导体层的下部形成高杂质浓度层，在侧面形成栅极绝缘膜所述突出半导体层的表面从所述第一绝缘层的上表面向上延伸，并且在所述栅极绝缘膜上和所述第一绝缘膜上形成栅电极。

10. 发明授权

US07662679B2 Semiconductor manufacturing method and semiconductor device 有权
标题翻译：半导体制造方法和半导体器件
公开(公告)号：US07662679B2
公开(公告)日：2010-02-16
申请号：US11203425
申请日：2005-08-15
申请人： Takashi Izumida , Sanae Ito , Takahisa Kanemura
发明人： Takashi Izumida , Sanae Ito , Takahisa Kanemura
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78609
摘要： A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
摘要翻译：制造半导体器件的方法包括在第一导电型半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成突出半导体层，在半导体衬底上形成第一绝缘层为了覆盖突出半导体层的下部，将第一导电型杂质掺杂到第一绝缘层中，从而在突出半导体层的下部形成高杂质浓度层，在侧面形成栅极绝缘膜所述突出半导体层的表面从所述第一绝缘层的上表面向上延伸，并且在所述栅极绝缘膜上和所述第一绝缘膜上形成栅电极。

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