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    • 3. 发明授权
    • Apparatus for rejecting time base error of video signal
    • 用于拒绝视频信号时基误差的装置
    • US5303061A
    • 1994-04-12
    • US894923
    • 1992-06-08
    • Tokikazu MatsumotoFumiaki KogaHiromu KitauraTakashi InoueNobuyuki Ogawa
    • Tokikazu MatsumotoFumiaki KogaHiromu KitauraTakashi InoueNobuyuki Ogawa
    • H04N5/956H04N9/89
    • H04N5/956
    • A time base correcting apparatus for reducing hindrance to a carrier chrominance signal due to clock jitter, when a sampling clock is generated by a digital circuit. In the time base correcting apparatus, a video signal is sampled with a clock synchronized with the video signal to be written to an FIFO memory. The video signal is then read out therefrom with a fixed clock to remove time base changes of the video signal. The fixed read clock is generated by multiplying two different frequency signals together, where one of the signals has a lower frequency approximately equal to (n+1/4) f (where n is an arbitrary integer, and f is a horizontal sync frequency) and using one of the resultant sidebands obtained through use of a bandpass filter. The read clock frequency is separated by 1/2 f from the other sideband frequency to reduce hindrance between the signals, and in turn to reduce viewable hindrances during the display of the video signal read out from the FIFO.
    • 一种时基校正装置,用于当由数字电路产生采样时钟时,减少由于时钟抖动对载波色度信号的阻碍。 在时基校正装置中,视频信号用与视频信号同步的时钟进行采样,以写入FIFO存储器。 然后以固定的时钟从其读出视频信号,以消除视频信号的时基变化。 固定读时钟通过将两个不同的频率信号相乘在一起而产生,其中一个信号具有近似等于(n + 1/4)f的较低频率(其中n是任意整数,f是水平同步频率) 并使用通过使用带通滤波器获得的所得边带之一。 读取时钟频率与另一个边带频率分开1/2 f,以减少信号之间的障碍,从而减少在从FIFO读出的视频信号的显示期间的可视障碍。
    • 5. 发明授权
    • Time base corrector having a velocity error data extracting circuit
    • 具有速度误差数据提取电路的时基校正器
    • US5229892A
    • 1993-07-20
    • US712041
    • 1991-06-07
    • Takashi InoueNobuyuki OgawaHiromu KitauraTokikazu Matsumoto
    • Takashi InoueNobuyuki OgawaHiromu KitauraTokikazu Matsumoto
    • H04N5/956
    • H04N5/956
    • A time base correcting circuit is provided in which a time base error in a video signal is corrected by converting the video signal to a digital form which is then recorded into a memory with a write-in clock signal synchronized with a horizontal synchronizing signal or a color burst signal carried in the video signal, reading the digital signal with a read-out clock signal generated from a reference clock signal, and converting it into an analog form. In particular, a velocity error data is added to a corresponding horizontal blanking period of the video signal and after processing of the signals having time delays and continuation errors in the time base, the velocity error data is extracted from the horizontal blanking period of the video signal. Then, the read-out clock signal is phase modulated with the velocity error data extracted and used for correction of the velocity error in the video signal of analog form converted from its digital form.
    • 提供了一种时基校正电路,其中通过将视频信号转换成数字形式来校正视频信号中的时基误差,该数字形式然后被记录到与水平同步信号同步的写入时钟信号的存储器中 视频信号中携带的彩色脉冲串信号,用从参考时钟信号产生的读出时钟信号读取数字信号,并将其转换为模拟形式。 特别地,速度误差数据被加到视频信号的相应的水平消隐周期中,并且在处理具有时间上的时间延迟和连续错误的信号之后,从视频的水平消隐周期中提取速度误差数据 信号。 然后,读取的时钟信号被提取出的速度误差数据进行相位调制,并用于校正从其数字形式转换的模拟形式的视频信号中的速度误差。