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1. 发明授权

US08397003B2 CPU connection circuit, data processing apparatus, arithmetic processing device, portable communication terminal using these modules and data transfer 有权
标题翻译： CPU连接电路，数据处理装置，算术处理装置，使用这些模块的便携式通信终端和数据传输
公开(公告)号：US08397003B2
公开(公告)日：2013-03-12
申请号：US13540225
申请日：2012-07-02
申请人： Takao Nakagawa , Takashi Tachikawa , Naoyuki Nakamura , Tadashi Tsukamoto , Toshikatsu Hosoi , Hiroshi Kurakane
发明人： Takao Nakagawa , Takashi Tachikawa , Naoyuki Nakamura , Tadashi Tsukamoto , Toshikatsu Hosoi , Hiroshi Kurakane
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F13/1673 , G06F13/4059
摘要： There are provided a CPU connection circuit and a method by two CPUs by alternately conducting a changeover between two buffers disposed there between to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.
摘要翻译：通过在两个CPU之间交替地进行两个缓冲器之间的切换来提供CPU连接电路和两个CPU的方法，以防止在接收侧的CPU不能完全执行数据处理的事件。包括存储器控制器，其监视由缓冲器301和302中的任一个中的CCPU 1存储的数据量是否达到预定阈值; 当CCPU1存储在缓冲器301,302中的数据量达到阈值时，存储器控制器请求ACPU 2获取存储在缓冲器中的数据，并将数据的存储目的地从CCPU改变到另一个的缓冲区; 该阈值是大于CCPU1发送到缓冲器301,302的单位数量的值。

2. 发明申请

US20110249560A1 CPU CONNECTION CIRCUIT, DATA PROCESSING APPARATUS, ARITHMETIC PROCESSING DEVICE, PORTABLE COMMUNICATION TERMINAL USING THESE MODULES AND DATA TRANSFER METHOD 有权
标题翻译： CPU连接电路，数据处理装置，算术处理装置，使用这些模块的便携式通信终端和数据传输方法
公开(公告)号：US20110249560A1
公开(公告)日：2011-10-13
申请号：US12374949
申请日：2007-07-25
申请人： Takao Nakagawa , Takashi Tachikawa , Naoyuki Nakamura , Tadashi Tsukamoto , Toshikatsu Hosoi , Hiroshi Kurakane
发明人： Takao Nakagawa , Takashi Tachikawa , Naoyuki Nakamura , Tadashi Tsukamoto , Toshikatsu Hosoi , Hiroshi Kurakane
IPC分类号： H04L12/26
CPC分类号： G06F13/1673 , G06F13/4059
摘要： There are provided a CPU connection circuit and a method wherein the CPU connection circuit is a circuit to be employed by two CPUs by alternately conducting a changeover between two buffers disposed therebetween to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller 303 which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller 303 requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.
摘要翻译：提供了一种CPU连接电路和一种方法，其中CPU连接电路是由两个CPU采用的电路，通过交替地在其间设置的两个缓冲器之间进行切换，以防止CPU在数据处理不能完全执行的事件接收方。包括存储器控制器303，其监视由缓冲器301和302中的任一个中的CCPU 1存储的数据量是否达到预定阈值; 当CCPU1存储在缓冲器301,302中的数据量达到阈值时，存储器控制器303请求ACPU 2获取存储在缓冲器中的数据，并将数据的存储目的地从CCPU改变到另一个其中一个缓冲区; 该阈值是大于CCPU1发送到缓冲器301,302的单位数量的值。

3. 发明授权

US08355326B2 CPU connection circuit, data processing apparatus, arithmetic processing device, portable communication terminal using these modules and data transfer method 有权
标题翻译： CPU连接电路，数据处理装置，算术处理装置，使用这些模块的便携式通信终端和数据传输方法
公开(公告)号：US08355326B2
公开(公告)日：2013-01-15
申请号：US12374949
申请日：2007-07-25
申请人： Takao Nakagawa , Takashi Tachikawa , Naoyuki Nakamura , Tadashi Tsukamoto , Toshikatsu Hosoi , Hiroshi Kurakane
发明人： Takao Nakagawa , Takashi Tachikawa , Naoyuki Nakamura , Tadashi Tsukamoto , Toshikatsu Hosoi , Hiroshi Kurakane
IPC分类号： H04L12/54
CPC分类号： G06F13/1673 , G06F13/4059
摘要： There are provided a CPU connection circuit and a method wherein the CPU connection circuit is a circuit to be employed by two CPUs by alternately conducting a changeover between two buffers disposed therebetween to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller 303 which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller 303 requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.
摘要翻译：提供了一种CPU连接电路和一种方法，其中CPU连接电路是由两个CPU采用的电路，通过交替地在其间设置的两个缓冲器之间进行切换，以防止CPU在数据处理不能完全执行的事件接收方。包括存储器控制器303，其监视由缓冲器301和302中的任一个中的CCPU 1存储的数据量是否达到预定阈值; 当CCPU1存储在缓冲器301,302中的数据量达到阈值时，存储器控制器303请求ACPU 2获取存储在缓冲器中的数据，并将数据的存储目的地从CCPU改变到另一个其中一个缓冲区; 该阈值是大于CCPU1发送到缓冲器301,302的单位数量的值。

4. 发明授权

US07437600B2 Method of data writing to and data reading from storage device and data storage system 有权
标题翻译：从存储设备和数据存储系统进行数据写入和数据读取的方法
公开(公告)号：US07437600B2
公开(公告)日：2008-10-14
申请号：US11060553
申请日：2005-02-18
申请人： Takashi Tachikawa
发明人： Takashi Tachikawa
IPC分类号： G06F11/00
CPC分类号： G06F11/108
摘要： Reliability of stored data in a semiconductor storage device such as a flash memory is enhanced. There are provided (n+1) physical storage regions each having m data storage areas and for which data writing, data reading, data erasure, and the like are collectively performed. A sequence of data input from a supervisory host as write data are rearranged, and that sequence of data is split across the n physical storage regions, for storage. Error correction data for the sequence of data 1 to data n split across the respective physical storage regions is stored in another (n+1)th physical storage region as data p1. Error correction data p2 for data (n+1) to data 2n, and error correction data pm for data ((m−1)n+1) to data mn are stored in the same manner. When abnormality is present in part or all of the data stored in a second physical storage region, for example, the data in the second physical storage region restored by error correction is stored in an alternative physical storage region, and the data in the second physical storage region are all erased.
摘要翻译：存储数据在闪速存储器等半导体存储装置中的可靠性得到提高。提供（n + 1）个物理存储区域，每个存储区域具有m个数据存储区域，并且共同执行数据写入，数据读取，数据擦除等。重新排列从监督主机输入的作为写入数据的数据序列，并且将数据序列分割在n个物理存储区域中以进行存储。数据1到数据n的分割跨越各物理存储区域的数据1的纠错数据被存储在第（n + 1）个物理存储区域中作为数据p 1。数据（n + 1）到数据2 n的纠错数据p 2以及数据（（m-1）n + 1）到数据mn的纠错数据pm以相同的方式存储。当存储在第二物理存储区域中的数据的部分或全部存在异常时，例如，通过纠错恢复的第二物理存储区域中的数据被存储在替代物理存储区域中，并且第二物理存储区域中的数据存储区域都被擦除。

5. 发明授权

US08803481B2 Battery pack and method of controlling the same 有权
标题翻译：电池组及其控制方法
公开(公告)号：US08803481B2
公开(公告)日：2014-08-12
申请号：US12683214
申请日：2010-01-06
申请人： Takashi Tachikawa , Masaki Hogari , Kiyohiko Watanabe
发明人： Takashi Tachikawa , Masaki Hogari , Kiyohiko Watanabe
IPC分类号： H02J7/00
CPC分类号： H01M10/4207 , H02J7/0031 , H02J7/0063 , H02J2007/0039
摘要： A battery pack for an electrically powered tool includes: one or plural secondary batteries connected in series and/or in parallel; a current detection resistor in a current path through which a charge/discharge current flows into each secondary battery; an N-channel charge control FET and an N-channel discharge control FET in the current path so as to control the charge/discharge current; and a controller detecting the charge/discharge current flowing in the current detection resistor and controlling the charge and discharge control FETs based on the detection result. A threshold value indicating an overcurrent detection current with respect to the charge/discharge current is set in advance, and the controller compares the charge/discharge current detected by the current detection resistor with the threshold value, and when the detected charge/discharge current is the threshold value or more, determines that an overcurrent state is detected and turns off the charge and discharge control FETs.
摘要翻译：一种用于电动工具的电池组包括：串联和/或并联连接的一个或多个二次电池; 电流路径中的电流检测电阻，充电/放电电流通过该电流检测电阻流入每个二次电池; 电流路径中的N沟道充电控制FET和N沟道放电控制FET，以控制充放电电流; 以及控制器，检测流过电流检测电阻器的充电/放电电流，并根据检测结果控制充放电控制FET。预先设定表示相对于充放电电流的过电流检测电流的阈值，并且控制器将由电流检测电阻器检测的充放电电流与阈值进行比较，并且当检测到的充电/放电电流为阈值以上确定检测到过电流状态，关闭充放电控制用FET。

6. 发明申请

US20100176764A1 BATTERY PACK AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：电池组及其控制方法
公开(公告)号：US20100176764A1
公开(公告)日：2010-07-15
申请号：US12683214
申请日：2010-01-06
申请人： Takashi Tachikawa , Masaki Hogari , Kiyohiko Watanabe
发明人： Takashi Tachikawa , Masaki Hogari , Kiyohiko Watanabe
IPC分类号： H02J7/00
CPC分类号： H01M10/4207 , H02J7/0031 , H02J7/0063 , H02J2007/0039
摘要： A battery pack for an electrically powered tool includes: one or plural secondary batteries connected in series and/or in parallel; a current detection resistor in a current path through which a charge/discharge current flows into each secondary battery; an N-channel charge control FET and an N-channel discharge control FET in the current path so as to control the charge/discharge current; and a controller detecting the charge/discharge current flowing in the current detection resistor and controlling the charge and discharge control FETs based on the detection result. A threshold value indicating an overcurrent detection current with respect to the charge/discharge current is set in advance, and the controller compares the charge/discharge current detected by the current detection resistor with the threshold value, and when the detected charge/discharge current is the threshold value or more, determines that an overcurrent state is detected and turns off the charge and discharge control FETs.
摘要翻译：一种用于电动工具的电池组包括：串联和/或并联连接的一个或多个二次电池; 电流路径中的电流检测电阻，充电/放电电流通过该电流检测电阻流入每个二次电池; 电流路径中的N沟道充电控制FET和N沟道放电控制FET，以控制充放电电流; 以及控制器，检测流过电流检测电阻器的充电/放电电流，并根据检测结果控制充放电控制FET。预先设定表示相对于充放电电流的过电流检测电流的阈值，并且控制器将由电流检测电阻器检测的充放电电流与阈值进行比较，并且当检测到的充放电电流为阈值以上确定检测到过电流状态，关闭充放电控制用FET。

7. 发明授权

US06191908B1 Thermal asperity compensating method, data reproduction error compensating method, automatic gain control system and magnetic disk unit 失效
标题翻译：热凹凸补偿方法，数据再现误差补偿方法，自动增益控制系统和磁盘单元
公开(公告)号：US06191908B1
公开(公告)日：2001-02-20
申请号：US09106310
申请日：1998-06-29
申请人： Takashi Tachikawa
发明人： Takashi Tachikawa
IPC分类号： G11B502
CPC分类号： G11B20/10009 , G11B5/012
摘要： A magnetic disk unit lowers a possibility to cause data reproduction errors by setting a gain of a variable gain amplifier (VGA) at a predetermined fixed level for a predetermined time when an output from the VGA which amplifies an input signal is changed to a value smaller than an optimum value upon occurrence of a thermal asperity and then restoring a variable gain condition so that an output amplitude automatically has a certain preset value.
摘要翻译：磁盘单元通过将可变增益放大器（VGA）的增益设定在预定的固定电平达预定时间来降低可能性，当放大输入信号的VGA的输出变为更小的值时比发生热凹凸时的最佳值，然后恢复可变增益条件，使得输出幅度自动具有一定的预设值。

8. 发明授权

US07518595B2 Pointing device control apparatus and method, electronic instrument, and computer program for the pointing device control apparatus 失效
标题翻译：指向装置控制装置和方法，电子仪器和用于指点装置控制装置的计算机程序
公开(公告)号：US07518595B2
公开(公告)日：2009-04-14
申请号：US10873458
申请日：2004-06-23
申请人： Takashi Tachikawa
发明人： Takashi Tachikawa
IPC分类号： G06F3/033 , G09G5/08
CPC分类号： G06F3/038
摘要： A control unit 203 controls a position of a pointer to be displayed on a display 208A in response to an operation of a pointing device (PD) 11 by the user. In this case, the control unit 203 detects actual operation directions 50 and 50′ of the PD 11 by means of a sensing module 13. Next, the control unit 203 determines whether or not the actual operation directions 50 and 50′ are included in an adjustment region 70, which is preset with a movable range of the PD 11 as an object to be adjusted. Then, when it is determined that the actual operation directions are included in the adjustment region 70, the control unit 203 adjusts information indicating the actual operation directions to information indicating a direction 60 so predetermined as to correspond to the adjustment region in such a way that a moving direction of the pointer displayed on the display 208A in response to the actual operation directions is changed to the predetermined direction.
摘要翻译：控制单元203响应于用户的指示设备（PD）11的操作来控制要在显示器208A上显示的指针的位置。在这种情况下，控制单元203通过感测模块13检测PD11的实际操作方向50和50'。接下来，控制单元203确定实际操作方向50和50'是否包括在调整区域70，其作为被调整对象的PD11的可移动范围被预先设定。然后，当确定实际操作方向包括在调整区域70中时，控制单元203将指示实际操作方向的信息调整为指示如预定的方向60的信息以对应于调节区域，使得响应于实际操作方向在显示器208A上显示的指针的移动方向被改变到预定方向。

9. 发明授权

US07040176B2 Design analysis method of earthquake-proof reinforcement structure, and storage medium 失效
公开(公告)号：US07040176B2
公开(公告)日：2006-05-09
申请号：US10007969
申请日：2001-12-06
申请人： Hajime Anzai , Takashi Tachikawa , Keijiro Yoshida , Hiroshi Sudo , Tomomichi Nakamura , Shigeru Ochiai
发明人： Hajime Anzai , Takashi Tachikawa , Keijiro Yoshida , Hiroshi Sudo , Tomomichi Nakamura , Shigeru Ochiai
IPC分类号： G01N3/00 , G06F19/00
CPC分类号： E04G23/0218 , E04B2001/2463 , E04H9/021 , G06F17/50 , G06F2217/34
摘要： A member of an earthquake-proof reinforcement structure is selected with reference to the allowable stress intensity ratio of the member, a ductility factor ratio allowable as a deformation magnification by earthquake-proof reinforcement of the selected member is set, an increase in load in a plasticity range, which acts on the selected member, is calculated on the basis of the set ductility factor ratio, and a corresponding allowable stress intensity ratio is obtained. When the obtained allowable stress intensity ratio is defined as a maximum value of 1.0, the corresponding increase in load in the plasticity range is specified as an ultimate load at which the selected member collapses.

10. 发明申请

US20050185476A1 Method of data writing to and data reading from storage device and data storage system 有权
标题翻译：从存储设备和数据存储系统进行数据写入和数据读取的方法
公开(公告)号：US20050185476A1
公开(公告)日：2005-08-25
申请号：US11060553
申请日：2005-02-18
申请人： Takashi Tachikawa
发明人： Takashi Tachikawa
IPC分类号： G06F12/16 , G06F11/10 , G11C5/00
CPC分类号： G06F11/108
摘要： Reliability of stored data in a semiconductor storage device such as a flash memory is enhanced. There are provided (n+1) physical storage regions each having m data storage areas and for which data writing, data reading, data erasure, and the like are collectively performed. A sequence of data input from a supervisory host as write data are rearranged, and that sequence of data is split across the n physical storage regions, for storage. Error correction data for the sequence of data 1 to data n split across the respective physical storage regions is stored in another (n+1)th physical storage region as data p1. Error correction data p2 for data (n+1) to data 2n, and error correction data pm for data ((m−1)n+1) to data mn are stored in the same manner. When abnormality is present in part or all of the data stored in a second physical storage region, for example, the data in the second physical storage region restored by error correction is stored in an alternative physical storage region, and the data in the second physical storage region are all erased.
摘要翻译：存储数据在闪速存储器等半导体存储装置中的可靠性得到提高。提供（n + 1）个物理存储区域，每个存储区域具有m个数据存储区域，并且共同执行数据写入，数据读取，数据擦除等。重新排列从监督主机输入的作为写入数据的数据序列，并且将数据序列分割在n个物理存储区域中以进行存储。将数据1的序列的数据1到数据n分割在各个物理存储区域的纠错数据作为数据p1存储在另一个第（n + 1）个物理存储区域中。对于数据（n + 1）到数据2n的纠错数据p2和数据（（m-1）n + 1）到数据mn的纠错数据pm以相同的方式存储。当存储在第二物理存储区域中的数据的部分或全部存在异常时，例如，通过纠错恢复的第二物理存储区域中的数据被存储在替代物理存储区域中，并且第二物理存储区域中的数据存储区域都被擦除。

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