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1. 发明授权

US08397003B2 CPU connection circuit, data processing apparatus, arithmetic processing device, portable communication terminal using these modules and data transfer 有权
标题翻译： CPU连接电路，数据处理装置，算术处理装置，使用这些模块的便携式通信终端和数据传输
公开(公告)号：US08397003B2
公开(公告)日：2013-03-12
申请号：US13540225
申请日：2012-07-02
申请人： Takao Nakagawa , Takashi Tachikawa , Naoyuki Nakamura , Tadashi Tsukamoto , Toshikatsu Hosoi , Hiroshi Kurakane
发明人： Takao Nakagawa , Takashi Tachikawa , Naoyuki Nakamura , Tadashi Tsukamoto , Toshikatsu Hosoi , Hiroshi Kurakane
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F13/1673 , G06F13/4059
摘要： There are provided a CPU connection circuit and a method by two CPUs by alternately conducting a changeover between two buffers disposed there between to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.
摘要翻译：通过在两个CPU之间交替地进行两个缓冲器之间的切换来提供CPU连接电路和两个CPU的方法，以防止在接收侧的CPU不能完全执行数据处理的事件。包括存储器控制器，其监视由缓冲器301和302中的任一个中的CCPU 1存储的数据量是否达到预定阈值; 当CCPU1存储在缓冲器301,302中的数据量达到阈值时，存储器控制器请求ACPU 2获取存储在缓冲器中的数据，并将数据的存储目的地从CCPU改变到另一个的缓冲区; 该阈值是大于CCPU1发送到缓冲器301,302的单位数量的值。

2. 发明授权

US08355326B2 CPU connection circuit, data processing apparatus, arithmetic processing device, portable communication terminal using these modules and data transfer method 有权
标题翻译： CPU连接电路，数据处理装置，算术处理装置，使用这些模块的便携式通信终端和数据传输方法
公开(公告)号：US08355326B2
公开(公告)日：2013-01-15
申请号：US12374949
申请日：2007-07-25
申请人： Takao Nakagawa , Takashi Tachikawa , Naoyuki Nakamura , Tadashi Tsukamoto , Toshikatsu Hosoi , Hiroshi Kurakane
发明人： Takao Nakagawa , Takashi Tachikawa , Naoyuki Nakamura , Tadashi Tsukamoto , Toshikatsu Hosoi , Hiroshi Kurakane
IPC分类号： H04L12/54
CPC分类号： G06F13/1673 , G06F13/4059
摘要： There are provided a CPU connection circuit and a method wherein the CPU connection circuit is a circuit to be employed by two CPUs by alternately conducting a changeover between two buffers disposed therebetween to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller 303 which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller 303 requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.
摘要翻译：提供了一种CPU连接电路和一种方法，其中CPU连接电路是由两个CPU采用的电路，通过交替地在其间设置的两个缓冲器之间进行切换，以防止CPU在数据处理不能完全执行的事件接收方。包括存储器控制器303，其监视由缓冲器301和302中的任一个中的CCPU 1存储的数据量是否达到预定阈值; 当CCPU1存储在缓冲器301,302中的数据量达到阈值时，存储器控制器303请求ACPU 2获取存储在缓冲器中的数据，并将数据的存储目的地从CCPU改变到另一个其中一个缓冲区; 该阈值是大于CCPU1发送到缓冲器301,302的单位数量的值。

3. 发明申请

US20120331190A1 CPU CONNECTION CIRCUIT, DATA PROCESSING APPARATUS, ARITHMETIC PROCESSING DEVICE, PORTABLE COMMUNICATION TERMINAL USING THESE MODULES AND DATA TRANSFER 有权
标题翻译： CPU连接电路，数据处理设备，算术处理设备，使用这些模块的便携式通信终端和数据传输
公开(公告)号：US20120331190A1
公开(公告)日：2012-12-27
申请号：US13540225
申请日：2012-07-02
申请人： Takao NAKAGAWA , Takashi TACHIKAWA , Naoyuki NAKAMURA , Tadashi TSUKAMOTO , Toshikatsu HOSOI , Hiroshi KURAKANE
发明人： Takao NAKAGAWA , Takashi TACHIKAWA , Naoyuki NAKAMURA , Tadashi TSUKAMOTO , Toshikatsu HOSOI , Hiroshi KURAKANE
IPC分类号： G06F5/14
CPC分类号： G06F13/1673 , G06F13/4059
摘要： There are provided a CPU connection circuit and a method by two CPUs by alternately conducting a changeover between two buffers disposed there between to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.
摘要翻译：通过在两个CPU之间交替地进行两个缓冲器之间的切换来提供CPU连接电路和两个CPU的方法，以防止在接收侧的CPU不能完全执行数据处理的事件。包括存储器控制器，其监视由缓冲器301和302中的任一个中的CCPU 1存储的数据量是否达到预定阈值; 当CCPU1存储在缓冲器301,302中的数据量达到阈值时，存储器控制器请求ACPU 2获取存储在缓冲器中的数据，并将数据的存储目的地从CCPU改变到另一个的缓冲区; 该阈值是大于CCPU1发送到缓冲器301,302的单位数量的值。

4. 发明申请

US20110249560A1 CPU CONNECTION CIRCUIT, DATA PROCESSING APPARATUS, ARITHMETIC PROCESSING DEVICE, PORTABLE COMMUNICATION TERMINAL USING THESE MODULES AND DATA TRANSFER METHOD 有权
标题翻译： CPU连接电路，数据处理装置，算术处理装置，使用这些模块的便携式通信终端和数据传输方法
公开(公告)号：US20110249560A1
公开(公告)日：2011-10-13
申请号：US12374949
申请日：2007-07-25
申请人： Takao Nakagawa , Takashi Tachikawa , Naoyuki Nakamura , Tadashi Tsukamoto , Toshikatsu Hosoi , Hiroshi Kurakane
发明人： Takao Nakagawa , Takashi Tachikawa , Naoyuki Nakamura , Tadashi Tsukamoto , Toshikatsu Hosoi , Hiroshi Kurakane
IPC分类号： H04L12/26
CPC分类号： G06F13/1673 , G06F13/4059
摘要： There are provided a CPU connection circuit and a method wherein the CPU connection circuit is a circuit to be employed by two CPUs by alternately conducting a changeover between two buffers disposed therebetween to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller 303 which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller 303 requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.
摘要翻译：提供了一种CPU连接电路和一种方法，其中CPU连接电路是由两个CPU采用的电路，通过交替地在其间设置的两个缓冲器之间进行切换，以防止CPU在数据处理不能完全执行的事件接收方。包括存储器控制器303，其监视由缓冲器301和302中的任一个中的CCPU 1存储的数据量是否达到预定阈值; 当CCPU1存储在缓冲器301,302中的数据量达到阈值时，存储器控制器303请求ACPU 2获取存储在缓冲器中的数据，并将数据的存储目的地从CCPU改变到另一个其中一个缓冲区; 该阈值是大于CCPU1发送到缓冲器301,302的单位数量的值。

5. 发明授权

US07085594B2 Portable telephone apparatus 失效
公开(公告)号：US07085594B2
公开(公告)日：2006-08-01
申请号：US09969658
申请日：2001-10-04
申请人： Toshikatsu Hosoi
发明人： Toshikatsu Hosoi
IPC分类号： H04M1/00 , H04B1/38 , H04B1/16 , H04B1/04
CPC分类号： H04M1/0262 , H04W52/0261 , Y02D70/00
摘要： The invention provides a portable telephone apparatus wherein, when a necessary voltage is not obtained from a cell because the cell is removed or consumed, data can be backed up with a simple configuration and at a low cost. A cell is removably accommodated in a cell accommodation portion of the body of a portable telephone apparatus, and the cell accommodation portion is closed up with a cell cover. Opening or closing of the cell cover is detected by a switch serving as a cell cover opening/closing detection apparatus in the body, and is outputted as an interrupt signal to a CPU through a control circuit. When the remaining power of the cell becomes little, a cell remaining power detection signal is outputted as another interrupt signal to the CPU through the control circuit. In response to either interrupt signal, stored data of a RAM are transferred to and protected by a flash ROM.

6. 发明授权

US07082288B2 Cellular phone, and data protection method and program thereof 失效
标题翻译：蜂窝电话及其数据保护方法及程序
公开(公告)号：US07082288B2
公开(公告)日：2006-07-25
申请号：US10323913
申请日：2002-12-20
申请人： Toshikatsu Hosoi
发明人： Toshikatsu Hosoi
IPC分类号： H04M1/00
CPC分类号： H04M1/0262 , H04M1/0214 , H04M1/0245 , H04M1/57 , H04M1/72522 , H04M1/72547 , H04M1/72561 , H04W52/0261 , Y02D70/00
摘要： When a casing opening/closing detection circuit detects folding of a casing, a control circuit transmits an interruption signal to a CPU. Upon reception of the interruption signal, the CPU backs up data, which is to be protected and stored in a RAM, by transferring it to a FLASH ROM through a bus. In addition, when a battery residual amount detection circuit detects that a battery residual amount has dropped below a predetermined value because it was left unattended for a long time, the information of detection is similarly transmitted through an interruption signal to the CPU. By using the CPU for executing backing-up, and by using a battery falling-off prevention lock to impose physical restrictions in order to prevent falling-off of a battery during use of a cellular phone, data loss caused by unexpected occurrence such as battery falling-off can be dealt with.
摘要翻译：当壳体打开/关闭检测电路检测到壳体的折叠时，控制电路将中断信号发送到CPU。在接收到中断信号时，CPU通过总线将其传送到FLASH ROM来备份要保护和存储在RAM中的数据。此外，当电池剩余量检测电路长时间无人值守时，电池剩余量检测电路检测到电池剩余量已经下降到预定值以下时，类似地通过中断信号向CPU发送检测信息。通过使用CPU执行备份，并且通过使用电池脱落防止锁来施加物理限制，以防止在使用蜂窝电话期间电池脱落，由意外发生的电池（例如电池）引起的数据丢失脱落可以处理。

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