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1. 发明授权

US5148247A Semiconductor device having trench isolation 失效
标题翻译：具有加速隔离的半导体器件
公开(公告)号：US5148247A
公开(公告)日：1992-09-15
申请号：US755596
申请日：1991-09-05
申请人： Takao Miura , Kazunori Imaoka
发明人： Takao Miura , Kazunori Imaoka
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763
CPC分类号： H01L21/763 , H01L21/76237
摘要： A semiconductor device having a trench isolation structure comprises a substrate, an active layer formed on the substrate, a trench which penetrates the active layer and reaches a portion of the substrate, and an insulator layer formed within the trench. The active layer has a region in which elements of the semiconductor device are formed, and the insulator layer has charges trapped in at least a predetermined portion thereof in a vicinity of the second region. This predetermined portion of the insulator layer has a depth which is greater than a depth of the region of the active layer.

2. 发明授权

US5250836A Semiconductor device having silicon-on-insulator structure 失效
标题翻译：具有绝缘体上硅结构的半导体器件
公开(公告)号：US5250836A
公开(公告)日：1993-10-05
申请号：US975897
申请日：1992-11-12
申请人： Takao Miura , Kazunori Imaoka
发明人： Takao Miura , Kazunori Imaoka
IPC分类号： H01L21/306 , H01L21/762 , H01L21/763 , H01L27/12
CPC分类号： H01L21/02052 , H01L21/76264 , H01L21/763 , H01L21/76267 , H01L21/76275 , H01L21/76281
摘要： A semiconductor device includes a first substrate made of a semiconductor, a first insulator layer which is formed on the first substrate, second substrate made of a semiconductor and formed on the first insulator layer, a trench which extends from a top surface of the second substrate to at least a part of the first insulator layer, and a second insulator layer which substantially defines a side wall of the trench.
摘要翻译：半导体器件包括由半导体制成的第一衬底，形成在第一衬底上的第一绝缘体层，由半导体制成并形成在第一绝缘体层上的第二衬底，从第二衬底的顶表面延伸的沟槽到第一绝缘体层的至少一部分，以及基本上限定沟槽的侧壁的第二绝缘体层。

3. 发明授权

US5231045A Method of producing semiconductor-on-insulator structure by besol process with charged insulating layers 失效
标题翻译：通过带电绝缘层的沉积工艺制造绝缘体上半导体结构的方法
公开(公告)号：US5231045A
公开(公告)日：1993-07-27
申请号：US728529
申请日：1991-07-11
申请人： Takao Miura , Kazunori Imaoka
发明人： Takao Miura , Kazunori Imaoka
IPC分类号： H01L21/20
CPC分类号： H01L21/2007 , Y10S148/012 , Y10S438/91
摘要： A method of producing a semiconductor-on-insulator structure generates a first fixed charge in an insulator layer of a base substrate. An active substrate which is made of a semiconductor is bonded on the insulator layer of the base substrate to thereby generate a second fixed charge at an interface of the insulator layer and the active substrate. The first and second fixed charges have mutually opposite polarities. A portion of the active substrate is removed to form the active substrate to an arbitrary thickness.
摘要翻译：制造绝缘体上半导体结构的方法在基底衬底的绝缘体层中产生第一固定电荷。由半导体制成的有源基板被接合在基底基板的绝缘体层上，从而在绝缘体层和有源基板的界面处产生第二固定电荷。第一和第二固定电荷具有相反的极性。去除活性基底的一部分以形成任意厚度的活性基底。

4. 发明授权

US5066993A Semiconductor device having semiconductor-on-insulator structure 失效
标题翻译：具有半导体绝缘体结构的半导体器件
公开(公告)号：US5066993A
公开(公告)日：1991-11-19
申请号：US447524
申请日：1989-12-07
申请人： Takao Miura , Kazunori Imaoka
发明人： Takao Miura , Kazunori Imaoka
IPC分类号： H01L21/20
CPC分类号： H01L21/2007
摘要： A method of producing a semiconductor-on-insulator structure generates a first fixed charge in an insulator layer of a base substrate. An active substrate which is made of a semiconductor is bonded on the insulator layer of the base substrate to thereby generate a second fixed charge at an interface of the insulator layer and the active substrate. The first and second fixed charges have mutually opposite polarities. A portion of the active substrate is removed to form the active substrate to an arbitrary thickness.

5. 发明授权

US5017998A Semiconductor device using SOI substrate 失效
标题翻译：使用SOI衬底的半导体器件
公开(公告)号：US5017998A
公开(公告)日：1991-05-21
申请号：US572597
申请日：1990-08-27
申请人： Takao Miura , Kazunori Imaoka , Fumitoshi Sugimoto
发明人： Takao Miura , Kazunori Imaoka , Fumitoshi Sugimoto
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763
CPC分类号： H01L21/76264 , H01L21/763 , H01L21/76275 , H01L21/76286
摘要： In a direct bonded SOI substrate where the SiO.sub.2 films OA, OB are respectively provided on the single surfaces of the silicon substrates A, B, at least any one of SiO.sub.2 films OA, OB has thickness of 1 .mu.m or more. These SiO.sub.2 films OA, OB are bonded and moreover the one silicon substrate B of such a bonded substrate is ground to thickness of about 1 .mu.m. A semiconductor device having a trench structure wherein the trench formed on the silicon substrate B passes through the interface between the SiO.sub.2 film OB and the SiO.sub.2 film OA. The bottom of such a trench is located within the SiO.sub.2 film OA and the bottom of the polycrystalline silicon conductive film within the trench is located within the SiO.sub.2 film OA rather than the interface between the silicon substrate B and SiO.sub.2 film OB.
摘要翻译：在SiO 2膜OA，OB分别设置在硅衬底A，B的单个表面上的直接键合SOI衬底中，SiO 2膜OA，OB中的至少任一个具有1μm或更大的厚度。这些SiO 2膜OA，OB接合，此外，将这种键合衬底的一个硅衬底B研磨成约1μm的厚度。具有沟槽结构的半导体器件，其中形成在硅衬底B上的沟槽穿过SiO 2膜OB和SiO 2膜OA之间的界面。这种沟槽的底部位于SiO 2膜OA内，并且沟槽内的多晶硅导电膜的底部位于SiO 2膜OA内，而不是硅衬底B和SiO 2膜OB之间的界面。

6. 发明授权

US4970568A Semiconductor device and a process for producing a semiconductor device 失效
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US4970568A
公开(公告)日：1990-11-13
申请号：US373591
申请日：1989-06-30
申请人： Takao Hiraguchi , Kazunori Imaoka
发明人： Takao Hiraguchi , Kazunori Imaoka
IPC分类号： H01L29/73 , H01L21/322 , H01L21/331 , H01L21/82 , H01L21/8238 , H01L23/556 , H01L27/06 , H01L27/092 , H01L29/167
CPC分类号： H01L29/167 , H01L21/3225 , H01L21/82 , H01L23/556 , H01L2924/0002 , Y10S148/024 , Y10S148/127
摘要： The present invention relates to semiconductor device, a e.g., a CMOS, comprising a denuded region and a bulk-defect region, as well as the process for producing, e.g., a CMOS. In a conventional CMOS, the distance (dp) between the bulk-defect region and P.sup.+ -type source of drain region--(dp)--is greater than the distance (dn) between the bulk--defect--region and the P well--(dn)--. As a result, a leakage current can be generated in the PN junction. In order to eliminate the problems caused due to dp>dn, the present invention forms in a--semiconductor-substrate a bulk-defect region having a depth which is nonuniform in accordance with the nonuniform depth of the semiconductor elements.
摘要翻译：本发明涉及包括裸露区域和体缺陷区域的半导体器件，例如CMOS，以及用于制造例如CMOS的工艺。在传统的CMOS中，体缺陷区域和漏区的P +型源之间的距离（dp） - （dp） - 大于体缺陷区和 P好 - （dn） - 。结果，可以在PN结中产生泄漏电流。为了消除由于dp> dn引起的问题，本发明在半导体衬底中形成根据半导体元件的不均匀深度具有不均匀深度的体缺陷区域。

7. 发明授权

US5094963A Process for producing a semiconductor device with a bulk-defect region having a nonuniform depth 失效
标题翻译：用于生产具有非均质深度的块状缺陷区的半导体器件的方法
公开(公告)号：US5094963A
公开(公告)日：1992-03-10
申请号：US577511
申请日：1990-09-05
申请人： Takao Hiraguchi , Kazunori Imaoka
发明人： Takao Hiraguchi , Kazunori Imaoka
IPC分类号： H01L29/73 , H01L21/322 , H01L21/331 , H01L21/82 , H01L21/8238 , H01L23/556 , H01L27/06 , H01L27/092 , H01L29/167
CPC分类号： H01L29/167 , H01L21/3225 , H01L21/82 , H01L23/556 , H01L2924/0002 , Y10S148/024 , Y10S148/127
摘要： The present invention relates to a semiconductor device e.g., a CMOS, comprising a denuded region and a bulk-defect region, as well as a process for producing, e.g., CMOS. In a conventional CMOS, the distance (dp) between the bulk-defect region and p.sup.+ -type source or drain region (dp) is greater than the distance (dn) between the bulk-defect region and the p well (dn). As a result, a leakage current can be generated in the PN junction. In order to eliminate the problems caused due to dp>dn, the present invention forms in a semiconductor substrate a bulk-defect region having a depth which is nonuniform in accordance with the nonuniform depth of the semiconductor elements.

8. 发明授权

US06232663B1 Semiconductor device having interlayer insulator and method for fabricating thereof 失效
标题翻译：具有层间绝缘体的半导体器件及其制造方法
公开(公告)号：US06232663B1
公开(公告)日：2001-05-15
申请号：US08904630
申请日：1997-08-01
申请人： Toshio Taniguchi , Kenji Nukui , Ibrahim Burki , Richard Huang , Simon Chan , Kazunori Imaoka , Kazutoshi Mochizuki
发明人： Toshio Taniguchi , Kenji Nukui , Ibrahim Burki , Richard Huang , Simon Chan , Kazunori Imaoka , Kazutoshi Mochizuki
IPC分类号： H01L2348
CPC分类号： H01L23/5329 , H01L21/76801 , H01L21/76804 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of fabricating thereof, including an insulator layer having alternately layered insulator films and boundary layers, wherein the boundary layers are more dense than the insulator films to prevent expansion and elongation of string-like defects across the boundary layers. The method includes mixing a nitrogen containing gas and a silane group gas to form an insulator film; temporarily stopping a flow of the silane group gas for approximately one to fifteen seconds to form a boundary layer over the insulator film; restarting the flow of the silane group gas; and repeating the steps of temporarily stopping and restarting for a predetermined number of times to form the plurality of alternately layered insulator films and boundary layers. The plurality of alternately layered insulator films and boundary layers is also etched at an etching rate for the insulator films greater than an etching rate for the boundary layers to form a step-shaped sloped opening.
摘要翻译：一种半导体器件及其制造方法，包括具有交替层叠的绝缘体膜和边界层的绝缘体层，其中边界层比绝缘膜更致密，以防止跨越边界层的线状缺陷的膨胀和伸长。该方法包括混合含氮气体和硅烷基气体以形成绝缘膜; 暂时停止硅烷气体流动约1至15秒，以在绝缘膜上形成边界层; 重新开始硅烷气体的流动; 并重复暂时停止并重新启动预定次数的步骤，以形成多个交替层叠的绝缘体膜和边界层。多个交替层叠的绝缘体膜和边界层也以对于绝缘体膜的蚀刻速率蚀刻大于边界层的蚀刻速率以形成阶梯形倾斜开口。

9. 发明授权

US5162254A Semiconductor device having a SOI substrate and fabrication method thereof 失效
标题翻译：具有SOI衬底的半导体器件及其制造方法
公开(公告)号：US5162254A
公开(公告)日：1992-11-10
申请号：US606956
申请日：1990-10-31
申请人： Shouji Usui , Taketoshi Inagaki , Kiyomasa Kamei , Takeshi Matsutani , Kazunori Imaoka
发明人： Shouji Usui , Taketoshi Inagaki , Kiyomasa Kamei , Takeshi Matsutani , Kazunori Imaoka
IPC分类号： H01L21/304 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/304 , H01L21/76264 , H01L21/84 , H01L29/78654 , H01L21/76275 , H01L21/76281 , Y10S148/135
摘要： A method for producing a semiconductor device on a semiconductor layer provided on an insulator layer comprises the steps of providing an opening on the semiconductor layer to expose a top surface of the insulator layer, depositing a first material layer that has a hardness exceeding the hardness of the semiconductor layer on the semiconductor layer including the exposed top surface, and patterning the first material layer such that a patterned region of the first inorganic material is left in the opening with a gap separating the patterned region from the side wall of the semiconductor layer. The method also comprises the steps of depositing a second material layer of a second inorganic material having a hardness substantially equal to the hardness of the semiconductor layer such that the second material layer covers the semiconductor layer including the opening wherein the patterned region of the first inorganic material is formed, said second material layer being deposited such that the second material layer covers the side wall of the opening and fills the gap between the side wall of the patterned region and the side wall of the opening, and lapping a top surface of the semiconductor layer that is covered by the second material layer, starting from a top surface of the second material layer and proceeding toward the insulator layer until a top surface of the patterned region of the first inorganic material is exposed.
摘要翻译：一种在设置在绝缘体层上的半导体层上制造半导体器件的方法，包括以下步骤：在半导体层上设置开口以露出绝缘体层的顶表面;沉积第一材料层，其硬度超过所述半导体层上的半导体层包括所述暴露的顶表面，以及对所述第一材料层进行图案化，使得所述第一无机材料的图案区域留在所述开口中，并使所述图案化区域与所述半导体层的侧壁分隔开。该方法还包括以下步骤：沉积具有基本上等于半导体层硬度的硬度的第二无机材料的第二材料层，使得第二材料层覆盖包括开口的半导体层，其中第一无机材料的图案化区域形成材料，所述第二材料层被沉积成使得第二材料层覆盖开口的侧壁并且填充图案化区域的侧壁和开口的侧壁之间的间隙，并且研磨该第一材料层的顶表面半导体层，其被第二材料层覆盖，从第二材料层的顶表面开始并朝向绝缘体层直到第一无机材料的图案化区域的顶表面露出。

10. 发明授权

US5075249A Method of making a BIC memory cell having contact openings with straight sidewalls and sharp-edge rims 失效
标题翻译：制造具有直线边界和夏普边缘的接触开口的BIC记忆体的方法
公开(公告)号：US5075249A
公开(公告)日：1991-12-24
申请号：US331193
申请日：1989-03-31
申请人： Noriaki Sato , Kazunori Imaoka
发明人： Noriaki Sato , Kazunori Imaoka
IPC分类号： H01L27/112 , G11C17/00 , H01L21/768 , H01L21/8246 , H01L27/115
CPC分类号： G11C17/00 , H01L21/76895 , H01L27/115
摘要： A BIC memory cell device comprises a first insulating layer covering a MOS structure, a first penetrating opening in the first insulating layer in correspondence to a drain region and defined by an inclined first side wall which defines the diameter of the first opening such that the diameter increases towards a top surface of the first insulating layer, a second penetrating opening in the first insulating layer in correspondence to a source region and defined by a second side wall having a straight vertical cross section, a third penetrating opening in the first insulating layer in correspondence to a gate electrode and defined by a third side wall having a straight vertical cross section, a second insulating layer provided on the first insulating layer in correspondence to the drain region, a first wiring electrode deposited such that the second insulating layer is sandwiched between the first wiring electrode and the drain region, and second and third wiring electrodes contacting with the source region and the gate electrode.

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