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    • 1. 发明授权
    • Sliding correlator
    • 滑动相关器
    • US5574754A
    • 1996-11-12
    • US556439
    • 1995-11-09
    • Takao KuriharaYoshitaka UchidaMasahiro Hamatsu
    • Takao KuriharaYoshitaka UchidaMasahiro Hamatsu
    • H04J13/00H04B1/7095H04L7/04H04L7/00
    • H04B1/7075H04B1/708H04B1/7085H04B1/7095H04L7/043
    • A sliding correlator for initial synchronization and tracking of a SS (Spread Spectrum)-modulated signal containing a transmitted pseudo noise (PN) code, digitizes the received signal, and attempts to correlate the PN code in the received signal with a locally generated reference PN code. Initial synchronization employs correlation with three reference PN codes, an early, center and late channel. When correlation is found between the transmitted PN code and one of the reference PN codes, the three reference PN codes are shifted to align the center channel with the correlated channel and to displace the early and late channel reference PN codes to one side and the other of the center channel. In one embodiment, the displacement is one-third chip, and in another embodiment, the displacement is one-half chip. In one embodiment for initial tracking, the three channels are displaced one chip from each other and, after failure to attain correlation in any of the channels, the three channels are displaced three chips to again seek synchronization. Initial Tracking, following initial synchronization, detects changes in correlation in the three channels, and adjust the frequency and/or the phase of the three reference PN codes to return the reference PN codes into a desired relationship with the transmitted PN code. In one embodiment of tracking, clockwise and counterclockwise cyclic permutation of the three reference PN codes is used to maintain alignment between the three reference PN codes and the transmitted PN code. In other embodiments, the condition of correlation, or lack thereof, in each channel is stored in a register and shifting of the reference PN codes is performed in response to the status of the register.
    • 用于初始同步和跟踪包含发射伪噪声(PN)码的SS(扩频))调制信号的滑动相关器对接收到的信号进行数字化,并尝试将接收信号中的PN码与本地生成的参考PN 码。 初始同步采用与三个参考PN码(早期,中心和晚期信道)的相关性。 当在所发送的PN码和参考PN码之一中发现相关时,三个参考PN码被移位以使中心信道与相关信道对准,并将早期和晚期信道参考PN码移位到一侧,而另一个 的中心渠道。 在一个实施例中,位移是三分之一芯片,在另一个实施例中,位移是二分之一芯片。 在初始跟踪的一个实施例中,三个信道彼此一个位移,并且在不能在任何信道中获得相关性之后,三个信道被移位三个码片以再次寻找同步。 初始跟踪在初始同步之后,检​​测三个通道中相关性的变化,并调整三个参考PN代码的频率和/或相位,以将参考PN代码返回到与发送的PN码的期望关系。 在跟踪的一个实施例中,使用三个参考PN码的顺时针和逆时针循环置换来保持三个参考PN码和所发送的PN码之间的对准。 在其他实施例中,每个信道中的相关条件或不存在的条件存储在寄存器中,并且响应于寄存器的状态执行参考PN码的移位。
    • 3. 发明授权
    • Maximum length shift register sequence generator
    • 最大长度移位寄存器序列发生器
    • US4864525A
    • 1989-09-05
    • US70491
    • 1987-07-07
    • Takao KuriharaMasahiro Hamatsu
    • Takao KuriharaMasahiro Hamatsu
    • H03K3/84H04L9/22
    • H03K3/84H04L9/0662H04L2209/12
    • A maximum length shift register sequence generator comprises: (1) an input terminal for feedback (FB 0); (2) an input terminal to the steering gate of the first stage (FB 1); (3) an output terminal from the exclusive OR gate of the last stage (CAS); (4) a three state output terminal from a multiplexer circuit (FB 2); and (5) a control input terminal of a three state output multiplexer circuit (FBCNT); a plurality of which can be connected in cascade. It includes a flipflop circuit, whose data input is a feedback control signal (FBCNT) controlling within which maximum length shift register sequence generator the output of the multiplexer circuit should be fedback, when they are connected in cascade, and whose clock input is the strobe pulse (STB), the output of this flipflop circuit being the enable input of the three state output multiplexer circuit. It includes further a logical product gate (AND 0), whose inputs are two signals, one being a latch enable pulse ( LE ) for latching, (i) the initial state of the flipflop, (ii) the feedback state, (iii) the last stage selection state for the flipflops, the other being a chip select (CS), and a demultiplexer circuit distributing the output of this logical product gate (AND 0) to the latch circuits for latching the data (i).about.(iii) described above, depending on the two select signals (SEL 0.about.1).
    • 最大长度移位寄存器序列发生器包括:(1)用于反馈的输入端(FB 0); (2)到第一级(FB 1)的转向门的输入端子; (3)来自最后级的异或门的输出端子(CAS); (4)来自多路复用器电路(FB2)的三态输出端子; 和(5)三状态输出多路复用器电路(&upbar&F)的控制输入端子; 其多个可以级联连接。 它包括一个触发器电路,其数据输入是一个反馈控制信号(& upbar&F),控制其中最大长度移位寄存器序列发生器,多路复用器电路的输出应该反馈,当它们串联连接时,其时钟输入为 选通脉冲(STB),该触发电路的输出是三态输出多路复用器电路的使能输入。 它还包括逻辑积门(AND 0),其输入是两个信号,一个是用于锁存的锁存使能脉冲(LE),(i)触发器的初始状态,(ii)反馈状态,(iii) 触发器的最后阶段选择状态,另一个是芯片选择(& upbar& C),以及将该逻辑积门(AND 0)的输出分配给锁存电路的解复用器电路,用于锁存数据(i)DIFFERENCE ),这取决于两个选择信号(SEL 0 DIFFERENCE 1)。
    • 7. 发明授权
    • Spread spectrum communication receiver
    • 扩频通信接收机
    • US5058128A
    • 1991-10-15
    • US485471
    • 1990-02-27
    • Takao KuriharaMasahiro Hamatsu
    • Takao KuriharaMasahiro Hamatsu
    • H04B1/707H04B1/7093
    • H04B1/7093H04B1/707
    • An SSC receiver, in which desired information is restored by means of a correlator, which forms the correlation between a received PN code included in a received signal and a reference PN code included in a reference signal, is disclosed, wherein it is so constructed that the output of the correlator stated above is inputted in pattern judging means, that in the case where no accordance with a predetermined judgment pattern is obtained, when a certain period of time has elapsed, judgment patterns, which are analogous to the predetermined judgment pattern stated above, are switched over one after another, every time a predetermined period of time has elapsed, and that the position, where the two codes are in accordance with each other, is set correctly by controlling the phase of the reference PN code by using the output, when the output of the correlator described above is in accordance with either one of the judgment patterns.
    • 公开了一种SSC接收机,其中通过相关器恢复期望信息,其形成包括在接收信号中的接收PN码与参考信号中包括的参考PN码之间的相关性,其中它被构造为使得 上述相关器的输出被输入到模式判断装置中,在不符合预定的判断模式的情况下,当经过一段时间时,与所述的预定判定模式类似的判断模式 如上所述,每隔一段时间经过一个接一个地切换,并且通过使用参考PN码的相位来控制两个码彼此相符的位置被正确地设置 当上述相关器的输出符合判断模式中的任一个时,输出。
    • 8. 发明授权
    • Maximum length shift register sequences generator
    • 最大长度移位寄存器序列发生器
    • US4785410A
    • 1988-11-15
    • US870204
    • 1986-06-02
    • Masahiro HamatsuTakao Kurihara
    • Masahiro HamatsuTakao Kurihara
    • H03K3/84H04J13/00H04J13/10H04L9/22G06F1/02
    • H04J13/0025H03K3/84H04J13/10H04L9/0662
    • A maximum length shift register sequence generator capable of changing the format and phase of an M code known as maximum length shift register sequences in the transmitter and receiver. The register is most suitable for use in spread spectrum communication systems adapted to effect transmission by correlation between an M code from the transmitter and such an M code generated in the receiver. The generator includes a latch for storing the format and initial phase of an M code to be generated subsequently, and a microprocessor for setting in the latch necessary data required for changing the M code. A change of the M code is effected by a strobe signal lasting for a time equal to the lasting time of one clock pulse.
    • 一种最大长度移位寄存器序列发生器,其能够改变在发射机和接收机中被称为最大长度移位寄存器序列的M码的格式和相位。 寄存器最适用于扩频通信系统,适用于通过发射机的M码与接收机中生成的M码之间的相关来实现发射。 发生器包括用于存储随后要产生的M代码的格式和初始相位的锁存器,以及用于设置锁存器需要改变M代码所需的数据的微处理器。 M代码的改变由持续一个等于一个时钟脉冲的持续时间的时间的选通信号来实现。