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    • 4. 发明授权
    • Spread spectrum receiving device
    • 扩频接收装置
    • US5285471A
    • 1994-02-08
    • US993378
    • 1992-12-18
    • Takao Kurihara
    • Takao Kurihara
    • H04B1/707H04L27/30H03D3/18H04L27/06
    • H04B1/709H04B1/707
    • A spread spectrum receiving device is disclosed, in which data demodulation is effected in such a way that a received signal is divided into two parts, from which a COS PN code chip signal and a SIN PN code chip signal are obtained; that these chip signals are A/D-converted by means of A/D converters and then given to digital correlators; and that correlation outputs thus obtained are combined to synthesize a final correlation output. Further there are disposed a plurality of steering gates on the input side of the A/D converters. The a/D conversion can be effected in the neighborhood of a point, where the level of PN code chip waveforms is stable, owing to the fact that the steering gates are controlled by control signals obtained by processing the correlation outputs or output of the A/D conversion. In this way it is made unnecessary to raise the sampling frequency for the A/D conversion and to increase the number of stages of shift registers in the digital correlators.
    • 公开了一种扩展频谱接收装置,其中以这样一种方式实现数据解调,使得接收信号被分成两部分,从中获得COS PN码片信号和SIN PN码片信号; 这些芯片信号通过A / D转换器进行A / D转换,然后给予数字相关器; 并且将由此获得的相关输出组合以合成最终的相关输出。 此外,在A / D转换器的输入侧设置多个转向门。 由于通过处理A相关输出或输出的相关输出或输出获得的控制信号来控制转向门,因此可以在PN码片波形的电平稳定的点附近实现a / D转换 / D转换。 以这种方式,不必提高A / D转换的采样频率并增加数字相关器中的移位寄存器的级数。
    • 9. 发明授权
    • Maximum length shift register sequence generator
    • 最大长度移位寄存器序列发生器
    • US4864525A
    • 1989-09-05
    • US70491
    • 1987-07-07
    • Takao KuriharaMasahiro Hamatsu
    • Takao KuriharaMasahiro Hamatsu
    • H03K3/84H04L9/22
    • H03K3/84H04L9/0662H04L2209/12
    • A maximum length shift register sequence generator comprises: (1) an input terminal for feedback (FB 0); (2) an input terminal to the steering gate of the first stage (FB 1); (3) an output terminal from the exclusive OR gate of the last stage (CAS); (4) a three state output terminal from a multiplexer circuit (FB 2); and (5) a control input terminal of a three state output multiplexer circuit (FBCNT); a plurality of which can be connected in cascade. It includes a flipflop circuit, whose data input is a feedback control signal (FBCNT) controlling within which maximum length shift register sequence generator the output of the multiplexer circuit should be fedback, when they are connected in cascade, and whose clock input is the strobe pulse (STB), the output of this flipflop circuit being the enable input of the three state output multiplexer circuit. It includes further a logical product gate (AND 0), whose inputs are two signals, one being a latch enable pulse ( LE ) for latching, (i) the initial state of the flipflop, (ii) the feedback state, (iii) the last stage selection state for the flipflops, the other being a chip select (CS), and a demultiplexer circuit distributing the output of this logical product gate (AND 0) to the latch circuits for latching the data (i).about.(iii) described above, depending on the two select signals (SEL 0.about.1).
    • 最大长度移位寄存器序列发生器包括:(1)用于反馈的输入端(FB 0); (2)到第一级(FB 1)的转向门的输入端子; (3)来自最后级的异或门的输出端子(CAS); (4)来自多路复用器电路(FB2)的三态输出端子; 和(5)三状态输出多路复用器电路(&upbar&F)的控制输入端子; 其多个可以级联连接。 它包括一个触发器电路,其数据输入是一个反馈控制信号(& upbar&F),控制其中最大长度移位寄存器序列发生器,多路复用器电路的输出应该反馈,当它们串联连接时,其时钟输入为 选通脉冲(STB),该触发电路的输出是三态输出多路复用器电路的使能输入。 它还包括逻辑积门(AND 0),其输入是两个信号,一个是用于锁存的锁存使能脉冲(LE),(i)触发器的初始状态,(ii)反馈状态,(iii) 触发器的最后阶段选择状态,另一个是芯片选择(& upbar& C),以及将该逻辑积门(AND 0)的输出分配给锁存电路的解复用器电路,用于锁存数据(i)DIFFERENCE ),这取决于两个选择信号(SEL 0 DIFFERENCE 1)。