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1. 发明授权

US06590809B2 Non-volatile semiconductor memory device 有权
公开(公告)号：US06590809B2
公开(公告)日：2003-07-08
申请号：US10040332
申请日：2002-01-09
申请人： Takanori Yamazoe , Hiroshi Yoshigi , Yoshiaki Kamigaki , Kozo Katayama , Shinichi Minami , Takeo Kanai
发明人： Takanori Yamazoe , Hiroshi Yoshigi , Yoshiaki Kamigaki , Kozo Katayama , Shinichi Minami , Takeo Kanai
IPC分类号： G11C1604
CPC分类号： G11C16/0433 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/26
摘要： When two bits are stored per memory cell and the two bits are written or read, writing or reading operation has to be performed twice. When a memory array is constructed by using a memory cell, by the access of twice, read time or write time twice as long as conventional read or write time is required. It causes deterioration in speed of a system using the memory. To solve the problem, according to the invention, bit arrangement of a conventional memory cell array is changed according to a writing or reading method With the configuration, a plurality of bytes can be simultaneously written or read by a single access. In order to perform reading at higher speed, a sense amplifier requiring no precharging is also provided.

2. 发明申请

US20060220100A1 Semicondudctor device 有权
标题翻译：半导体器件
公开(公告)号：US20060220100A1
公开(公告)日：2006-10-05
申请号：US11415129
申请日：2006-05-02
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

3. 发明申请

US20050258474A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050258474A1
公开(公告)日：2005-11-24
申请号：US10484578
申请日：2002-07-22
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L29/423 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

4. 发明授权

US06531735B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06531735B1
公开(公告)日：2003-03-11
申请号：US09660923
申请日：2000-09-13
申请人： Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
发明人： Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
IPC分类号： H01L29792
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L21/28273 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.
摘要翻译：高密度，高速度和高可靠性的多存储非易失性存储器具有置于存储晶体管的两侧的存储晶体管和开关晶体管。存储晶体管包括具有离散陷阱和存储栅电极的栅极绝缘膜，而开关晶体管包括开关栅电极。栅极绝缘膜具有用于存储信息电荷的离散陷阱，可以局部注入载流子，并且一个存储器单元构成用于至少存储2位信息的多存储单元。具有开关栅电极的开关晶体管实现源极侧注入。存储晶体管与自对准扩散中的开关晶体管一起发生。存储晶体管的存储栅电极连接到字线，以便执行字线擦除。

5. 发明申请

US20060102967A1 Semiconductor integrated circuit 失效
公开(公告)号：US20060102967A1
公开(公告)日：2006-05-18
申请号：US11320850
申请日：2005-12-30
申请人： Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
发明人： Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
IPC分类号： H01L29/76
CPC分类号： G11C16/0475 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42332 , H01L29/7887
摘要： A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

6. 发明授权

US06936888B2 Nonvolatile memory device with multi-bit memory cells having plural side gates 有权
标题翻译：具有多个存储单元的非易失性存储器件具有多个侧栅极
公开(公告)号：US06936888B2
公开(公告)日：2005-08-30
申请号：US10676158
申请日：2003-10-02
申请人： Kozo Katayama , Yoshiaki Kamigaki , Shinichi Minami
发明人： Kozo Katayama , Yoshiaki Kamigaki , Shinichi Minami
IPC分类号： B42D15/10 , G06K19/07 , G06K19/077 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/14 , G11C16/26 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L27/115 , G11C16/0475 , G11C16/10 , G11C16/14 , G11C16/26 , H01L29/7923
摘要： A nonvolatile memory device has a plurality of nonvolatile memory cells in which a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side to store information in the memory cells. The memory gate electrode and the switch gate electrodes extend in the same direction. The application of a high electric field to a memory cell which is not selected for writing can be avoided owing to the switch gate electrodes being held in a cut-off state.
摘要翻译：非易失性存储器件具有多个非易失性存储单元，其中存储栅极电极形成在第一半导体区域上，栅极绝缘膜和栅极氮化物膜介于其间。第一和第二开关栅电极以及用作源/漏电极的第一和第二信号电极形成在存储栅电极的两侧。从源极将电子注入到栅极氮化物膜中，以将信息存储在存储单元中。存储栅电极和开关栅电极沿相同方向延伸。由于开关栅极被保持在截止状态，因此可以避免对未被选择用于写入的存储单元施加高电场。

7. 发明申请

US20100157689A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100157689A1
公开(公告)日：2010-06-24
申请号：US12718111
申请日：2010-03-05
申请人： TOSHIHIRO TANAKA , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： TOSHIHIRO TANAKA , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： G11C16/06 , H01L29/788 , G11C16/04
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

8. 发明授权

US07700992B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07700992B2
公开(公告)日：2010-04-20
申请号：US12142566
申请日：2008-06-19
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

9. 发明授权

US06894344B2 Semiconductor integrated circuit having two switch transistors formed between two diffusion-layer lines 失效
标题翻译：具有形成在两个扩散层线之间的两个开关晶体管的半导体集成电路
公开(公告)号：US06894344B2
公开(公告)日：2005-05-17
申请号：US10663779
申请日：2003-09-17
申请人： Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
发明人： Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
IPC分类号： G11C11/56 , G11C16/02 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/02 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L21/28273 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.
摘要翻译：高密度，高速度和高可靠性的多存储非易失性存储器具有置于存储晶体管的两侧的存储晶体管和开关晶体管。存储晶体管包括具有离散陷阱和存储栅电极的栅极绝缘膜，而开关晶体管包括开关栅电极。栅极绝缘膜具有用于存储信息电荷的离散陷阱，可以局部注入载流子，并且一个存储器单元构成用于至少存储2位信息的多存储单元。具有开关栅电极的开关晶体管实现源极侧注入。存储晶体管与自对准扩散中的开关晶体管一起发生。存储晶体管的存储栅电极连接到字线，以便执行字线擦除。

10. 发明授权

US06653685B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US06653685B2
公开(公告)日：2003-11-25
申请号：US09988725
申请日：2001-11-20
申请人： Kozo Katayama , Yoshiaki Kamigaki , Shinichi Minami
发明人： Kozo Katayama , Yoshiaki Kamigaki , Shinichi Minami
IPC分类号： H01L29792
CPC分类号： H01L27/115 , G11C16/0475 , G11C16/10 , G11C16/14 , G11C16/26 , H01L29/7923
摘要： A nonvolatile memory device has a plurality of nonvolatile memory cells in which a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side to store information in the memory cells. The memory gate electrode and the switch gate electrodes extend in the same direction. The application of a high electric field to a memory cell which is not selected for writing can be avoided owing to the switch gate electrodes being held in a cut-off state.
摘要翻译：非易失性存储器件具有多个非易失性存储单元，其中存储栅极电极形成在第一半导体区域上，栅极绝缘膜和栅极氮化物膜介于其间。第一和第二开关栅电极以及用作源/漏电极的第一和第二信号电极形成在存储栅电极的两侧。从源极将电子注入到栅极氮化物膜中，以将信息存储在存储单元中。存储栅电极和开关栅电极沿相同方向延伸。由于开关栅极被保持在截止状态，因此可以避免对未被选择用于写入的存储单元施加高电场。

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