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1. 发明授权

US5780866A Method and apparatus for automatic focusing and a method and apparatus for three dimensional profile detection 失效
标题翻译：自动对焦的方法和装置以及用于三维轮廓检测的方法和装置
公开(公告)号：US5780866A
公开(公告)日：1998-07-14
申请号：US559946
申请日：1995-11-17
申请人： Hisae Yamamura , Yukio Matsuyama , Takanori Ninomiya , Hideaki Sasazawa
发明人： Hisae Yamamura , Yukio Matsuyama , Takanori Ninomiya , Hideaki Sasazawa
IPC分类号： G01B11/02 , G01B11/24 , G01C3/06 , G01N21/956 , G01R31/309 , G06T1/00 , G01N21/84
CPC分类号： G01R31/309 , G01B11/026 , G01B11/24 , G01N21/956
摘要： A method for automatic focusing and three dimensional profile detection and an apparatus for automatic focusing and three dimensional profile detection have the purpose of detecting a three dimensional profile of the state of mounting of parts or soldering on a board without the affects of warp, even if the board of the detection object is warped, as if the surface of the board were on a flat plane. The board surface height is detected in a plurality of windows corresponding to stage scanning regions from a three dimensional profile signal of the part-mounted board detected by a height detection optical system. The board height or inclination in the next window is forecasted from the board surface height and the control history of stage height in the already-detected plurality of windows. Based on the forecasted board surface height or inclination, the speed or height in the Z direction of a Z-stage is controlled according to a feedforward method with scanning so as that the board surface and the focal plane of the height detection optical system are made coincident.
摘要翻译：用于自动聚焦和三维轮廓检测的方法以及用于自动聚焦和三维轮廓检测的装置的目的是检测零件的安装状态或焊接在板上的三维轮廓，而不影响翘曲，即使检测对象的板翘曲，仿佛板的表面在平面上。根据由高度检测光学系统检测的部件安装板的三维轮廓信号，在与台架扫描区域相对应的多个窗口中检测板表面高度。在已经检测到的多个窗口中，从板表面高度和台架高度的控制历史预测下一窗口中的板高度或倾斜度。基于预测的板表面高度或倾斜度，根据前馈方法控制Z级Z方向的速度或高度，以使得高度检测光学系统的板表面和焦平面成为巧合

2. 发明授权

US5459794A Method and apparatus for measuring the size of a circuit or wiring pattern formed on a hybrid integrated circuit chip and a wiring board respectively 失效
标题翻译：分别测量形成在混合集成电路芯片和布线板上的电路或布线图案的尺寸的方法和装置
公开(公告)号：US5459794A
公开(公告)日：1995-10-17
申请号：US91381
申请日：1993-07-15
申请人： Takanori Ninomiya , Hisae Yamamura
发明人： Takanori Ninomiya , Hisae Yamamura
IPC分类号： G01B11/02 , G06T7/60 , G06K9/00 , G01J4/00 , H04N7/18
CPC分类号： G06T7/602 , G01B11/022 , G06T2207/30141
摘要： A measuring method and apparatus for automatically and accurately measuring the sizes of portions of a hybrid integrated circuit chip and circuit patterns formed thereon or a wiring board and wiring patterns formed thereon. An image of a portion of a hybrid integrated circuit chip or wiring board is obtained through a TV camera which provides image signals representing images including those of objective portions. The image signals are processed to calculate the positions of the objective portions automatically. The size of an arbitrary objective portion is determined from a difference between respective positions of other objective portions.
摘要翻译：一种测量方法和装置，用于自动和精确地测量混合集成电路芯片和形成在其上的电路图案的部分的尺寸或布线板以及其上形成的布线图案。混合集成电路芯片或布线板的一部分的图像通过提供表示包括目标部分的图像的图像的图像信号的TV摄像机获得。处理图像信号以自动计算物镜部分的位置。任意目标部分的大小由其他目标部分的各个位置之间的差确定。

3. 发明授权

US06333992B1 Defect judgement processing method and apparatus 失效
标题翻译：缺陷判断处理方法和装置
公开(公告)号：US06333992B1
公开(公告)日：2001-12-25
申请号：US08967015
申请日：1997-11-10
申请人： Hisae Yamamura , Yukio Matsuyama , Toshifumi Honda , Ludwig Listl
发明人： Hisae Yamamura , Yukio Matsuyama , Toshifumi Honda , Ludwig Listl
IPC分类号： G06K900
CPC分类号： G01N21/88 , G01N21/956
摘要： A defect judgement processing method and apparatus which can optimize image processing and defect judgement parameters for a detection image cut out by each inspection window to avoid erroneous judgement and defect missing and to realize reliable defect judgement. An image data generator cuts out ranges indicated by a plurality of predesignated inspection windows from a detected image and stores them in a memory, a window data generator generates window data having inspection conditions attached thereto with respect to the plurality of inspection windows and stores them in the memory, a feature extractor reads out detection images of the ranges indicated by the inspection windows from the memory and extracts a structural feature parameter therefrom on the basis of an image processing parameter conforming to the inspection condition obtained by the window data, and a defect judger performs its defect judging operation over the extracted structural feature parameter on the basis of a defect judgement parameter conforming to the inspection condition.
摘要翻译：一种缺陷判断处理方法和装置，其可以优化每个检查窗口切出的检测图像的图像处理和缺陷判断参数，以避免错误判断和缺陷缺失，并实现可靠的缺陷判断。图像数据发生器从检测到的图像中切出由多个预先指定的检查窗口指示的范围并将其存储在存储器中，窗口数据生成器生成具有关于多个检查窗口附加到其上的检查条件的窗口数据，并将它们存储在存储器中，特征提取器基于从窗口数据获得的检查条件的图像处理参数，从存储器读出由检查窗口指示的范围的检测图像，并从其提取结构特征参数，并且缺陷基于符合检查条件的缺陷判断参数，判断器对提取的结构特征参数执行缺陷判断操作。

4. 发明授权

US06622054B1 Method monitoring a quality of electronic circuits and its manufacturing condition and system for it 失效
标题翻译：监控电子电路质量的方法及其制造条件和系统
公开(公告)号：US06622054B1
公开(公告)日：2003-09-16
申请号：US09413468
申请日：1999-10-06
申请人： Hirohito Okuda , Toshifumi Honda , Hisae Yamamura , Yuji Takagi , Hideaki Doi , Shigeshi Yoshinaga
发明人： Hirohito Okuda , Toshifumi Honda , Hisae Yamamura , Yuji Takagi , Hideaki Doi , Shigeshi Yoshinaga
IPC分类号： G05B1302
CPC分类号： G05B19/41875 , G05B23/0216 , G05B23/024 , G05B2219/37572 , G05B2219/45029 , H05K1/0269 , H05K3/0005 , H05K3/3484 , Y02P90/04 , Y02P90/22
摘要： With a view to providing a monitoring system for the quality and manufacturing conditions of electronic circuits capable of facilitating the grasping of correlation's between diverse manufacturing conditions and manufacturing states, statistically characteristic images are selected out of a group of images retrieved from a detection information database by specifying at least one out of the values of feature quantities, design information and manufacturing conditions, and are displayed.
摘要翻译：为了提供电子电路的质量和制造条件的监测系统，能够便于掌握不同的制造条件和制造状态之间的相关性，从通过检测信息数据库检索的一组图像中选出统计特征图像指定特征量，设计信息和制造条件的值中的至少一个，并且被显示。

5. 发明授权

US5373471A Semiconductor memory device having redundancy memory cells for replacing defective 失效
标题翻译：具有用于替换有缺陷的冗余存储单元的半导体存储器件
公开(公告)号：US5373471A
公开(公告)日：1994-12-13
申请号：US934332
申请日：1992-08-25
申请人： Makoto Saeki , Kiyoshi Nagai , Hisae Yamamura , Tadashi Abe , Takeshi Fukazawa
发明人： Makoto Saeki , Kiyoshi Nagai , Hisae Yamamura , Tadashi Abe , Takeshi Fukazawa
IPC分类号： G11C11/413 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/846
摘要： In case an address is to access a defective memory cell, a defective memory cell in a memory cell area contained in one of paired memory mats is selected in parallel with a redundant memory cell in a redundant memory cell area contained in the other memory mat. At this time of selecting the redundant main word line for selecting the redundant memory cell, there is not required the logical operation for deciding whether or not the redundant use of the access address fed from the outside is proper. For example, the redundant main word line is set to the select level on the basis of a chip select signal. As a result, the drive start timing of the redundant main word line is not delayed in the least from the drive start timing of the main word line. Thus, it is possible to prevent the event that the select drive timing of the redundant sub word line is delayed on account of the delay in the drive timing of the redundant main word line.
摘要翻译：在地址要访问有缺陷的存储单元的情况下，在包含在其中一个存储器堆中的存储单元区域中的有缺陷的存储器单元与冗余存储器单元并联地选择在另一存储器堆中所包含的冗余存储单元区域中。在选择用于选择冗余存储单元的冗余主字线时，不需要用于判断从外部馈送的访问地址的冗余使用是否合适的逻辑操作。例如，基于片选信号将冗余主字线设定为选择电平。结果，冗余主字线的驱动开始定时至少不会从主字线的驱动开始定时延迟。因此，可以防止由于冗余主字线的驱动定时的延迟而使冗余子字线的选择驱动定时被延迟的事件。

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