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1. 发明授权

US08738892B2 Very long instruction word (VLIW) computer having efficient instruction code format 有权
标题翻译：超长指令字（VLIW）计算机具有有效的指令码格式
公开(公告)号：US08738892B2
公开(公告)日：2014-05-27
申请号：US12103372
申请日：2008-04-15
申请人： Takahiro Kageyama , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
发明人： Takahiro Kageyama , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
IPC分类号： G06F15/00
CPC分类号： G06F9/3853 , G06F9/30145 , G06F9/30156 , G06F9/3016 , G06F9/3822 , G06F9/3885
摘要： A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.
摘要翻译：具有缩小尺寸的指令集的超长指令字（VLIW）处理器，导致指定寄存器所需的少量位。 VLIW处理器包括寄存器文件和第一至第三操作单元，并且执行非常长的指令字。此外，非常长的指令字包括指定寄存器文件中的至少一个寄存器和多个指令的寄存器指定字段。每个指令的操作数包括位src1，src2和dst，它们指示由寄存器指定字段指定的寄存器是否用作源寄存器和目标寄存器。

2. 发明授权

US07383422B2 Very long instruction word (VLIW) computer having an efficient instruction code format 有权
标题翻译：非常长的指令字（VLIW）计算机具有有效的指令码格式
公开(公告)号：US07383422B2
公开(公告)日：2008-06-03
申请号：US10949230
申请日：2004-09-27
申请人： Takahiro Kageyama , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
发明人： Takahiro Kageyama , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
IPC分类号： G06F15/76
CPC分类号： G06F9/3853 , G06F9/30145 , G06F9/30156 , G06F9/3016 , G06F9/3822 , G06F9/3885
摘要： A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.
摘要翻译：具有缩小尺寸的指令集的超长指令字（VLIW）处理器，导致指定寄存器所需的少量位。 VLIW处理器包括寄存器文件和第一至第三操作单元，并且执行非常长的指令字。此外，非常长的指令字包括指定寄存器文件中的至少一个寄存器和多个指令的寄存器指定字段。每个指令的操作数包括位src 1，src 2和dst，它们指示由寄存器指定字段指定的寄存器是否用作源寄存器和目标寄存器。

3. 发明申请

US20050182916A1 Processor and compiler 有权
标题翻译：处理器和编译器
公开(公告)号：US20050182916A1
公开(公告)日：2005-08-18
申请号：US10949230
申请日：2004-09-27
申请人： Takahiro Kageyama , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
发明人： Takahiro Kageyama , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
IPC分类号： G06F9/38 , G06F9/30 , G06F9/34 , G06F9/45 , G06F15/00
CPC分类号： G06F9/3853 , G06F9/30145 , G06F9/30156 , G06F9/3016 , G06F9/3822 , G06F9/3885
摘要： A VLIW processor which has an instruction set whose size is reduced so that a small number of bits are necessary to specify registers is provided. The VLIW processor 10 comprises the register file 12, the first-the third operation units 14a-14c and the like, and executes the very long instruction word. And, the very long instruction word includes the register specifying field which specifies a least one of the registers in the register file 12 and a plurality of instructions. The operand of each instruction has the bits, src1 src2 and dst, indicating whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.
摘要翻译：提供了具有指令集的VLIW处理器，其大小被减小以便需要少量位来指定寄存器。 VLIW处理器10包括寄存器文件12，第一个第三操作单元14 a-14 c等，并且执行非常长的指令字。并且，长指令字包括指定寄存器文件12中的至少一个寄存器的寄存器指定字段和多个指令。每个指令的操作数都有位src 1 src 2和dst，表示由寄存器指定字段指定的寄存器是否用作源寄存器和目的寄存器。

4. 发明申请

US20080201560A1 VERY LONG INSTRUCTION WORD (VLIW) COMPUTER HAVING EFFICIENT INSTRUCTION CODE FORMAT 有权
标题翻译：具有有效指导代码格式的非常长的指令词（VLIW）计算机
公开(公告)号：US20080201560A1
公开(公告)日：2008-08-21
申请号：US12103372
申请日：2008-04-15
申请人： Takahiro KAGEYAMA , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
发明人： Takahiro KAGEYAMA , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/30145 , G06F9/30156 , G06F9/3016 , G06F9/3822 , G06F9/3885
摘要： A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.
摘要翻译：具有缩小尺寸的指令集的超长指令字（VLIW）处理器，导致指定寄存器所需的少量位。 VLIW处理器包括寄存器文件和第一至第三操作单元，并且执行非常长的指令字。此外，非常长的指令字包括指定寄存器文件中的至少一个寄存器和多个指令的寄存器指定字段。每个指令的操作数包括位src 1，src 2和dst，它们指示由寄存器指定字段指定的寄存器是否用作源寄存器和目标寄存器。

5. 发明授权

US07594099B2 Processor executing SIMD instructions 有权
标题翻译：处理器执行SIMD指令
公开(公告)号：US07594099B2
公开(公告)日：2009-09-22
申请号：US11896368
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/305
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC0〜VC3（110）全部为零，并且（i）设置条件标志C4 当所有向量条件标志VC0〜VC3都为零时，分别将条件标志寄存器（CFR）32至1和0分别设置为条件标志寄存器（CFR）32和C5，以及（ii）分别将条件标志C4和C5设置为0和1，并非所有向量条件标志都为零。然后，矢量条件标志VC0〜VC3被存储在条件标志C0〜C3中。

6. 发明申请

US20080046704A1 Processor executing SIMD instructions 审中-公开
标题翻译：处理器执行SIMD指令
公开(公告)号：US20080046704A1
公开(公告)日：2008-02-21
申请号：US11896371
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki OKabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki OKabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/38
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

7. 发明申请

US20080046687A1 Processor executing SIMD instructions 有权
公开(公告)号：US20080046687A1
公开(公告)日：2008-02-21
申请号：US11896368
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/302 , G06F15/80
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

8. 发明申请

US20050216699A1 Parallel operation processor 有权
标题翻译：并行运算处理器
公开(公告)号：US20050216699A1
公开(公告)日：2005-09-29
申请号：US11054049
申请日：2005-02-09
申请人： Takeshi Tanaka , Hideshi Nishida , Masashi Hoshino , Takeshi Furuta
发明人： Takeshi Tanaka , Hideshi Nishida , Masashi Hoshino , Takeshi Furuta
IPC分类号： G06F9/318 , G06F9/38 , G06F15/00 , G06F15/80
CPC分类号： G06F9/3885 , G06F9/30181 , G06F9/3824 , G06F9/3826 , G06F9/3828 , G06F9/3887 , G06F15/8015
摘要： A processor having a plurality of processing elements and a decoder operable to decode an instruction. Each of the plurality of processing elements includes: a transfer pattern storage unit operable to store a transfer pattern value that indicates a processing element from which data is transferred; a transfer unit operable to perform a data transfer from the processing element indicated by the transfer pattern value; and an update unit operable to update the transfer pattern value stored in the transfer pattern storage unit, in accordance with a result of decoding a latest instruction by the decoder.
摘要翻译：具有多个处理元件的处理器和可解码指令的解码器。多个处理元件中的每一个包括：传送图案存储单元，用于存储指示从其传送数据的处理元件的传送图案值; 传送单元，其可操作以从由所述传送图案值指示的处理单元执行数据传送; 以及更新单元，用于根据由解码器解码最新指令的结果来更新存储在传送模式存储单元中的传送模式值。

9. 发明申请

US20050138326A1 SIMD type parallel operation apparatus used for parallel operation of image signal or the like 审中-公开
标题翻译：用于图像信号等的并行操作的SIMD型并行操作装置
公开(公告)号：US20050138326A1
公开(公告)日：2005-06-23
申请号：US11009056
申请日：2004-12-13
申请人： Kengo Terada , Takeshi Tanaka , Hideshi Nishida
发明人： Kengo Terada , Takeshi Tanaka , Hideshi Nishida
IPC分类号： G06F12/02 , G06F12/00 , G06F15/00 , G06F15/80 , G06T1/20
CPC分类号： G06T1/20 , G06F9/30181 , G06F9/345 , G06F9/3885 , G06F9/3887
摘要： A parallel operation apparatus of a SIMD type comprises a processor element group of the SIMD type including a plurality of processor elements, wherein the respective processor elements simultaneously execute an identical operation, a data memory accessible from the respective processor elements in the processor element group, and an address conversion unit for converting an address with respect to the data memory accessed by the processor elements in accordance with a control signal by changing bit positions of the address. The address conversion unit preferably rearranges a first bit, a second bit, and a third bit from a lower order of address data into the second bit, the third bit, and the first bit from the lower order in the change of the bit positions.
摘要翻译： SIMD类型的并行操作装置包括包括多个处理器元件的SIMD类型的处理器元件组，其中相应的处理器元件同时执行相同的操作，可从处理器元件组中的相应处理器元件访问的数据存储器，以及地址转换单元，用于通过改变地址的位位置来根据控制信号转换相对于由处理器单元访问的数据存储器的地址。地址转换单元优选地从比特位置的改变中的低阶地址将第一比特，第二比特和第三比特从地址数据的较低阶重新排列成第二比特，第三比特和第一比特。

10. 发明申请

US20090228691A1 ARITHMETIC PROCESSING APPARATUS 有权
标题翻译：算术处理装置
公开(公告)号：US20090228691A1
公开(公告)日：2009-09-10
申请号：US11720899
申请日：2005-08-24
申请人： Takeshi Furuta , Hideshi Nishida , Takeshi Tanaka
发明人： Takeshi Furuta , Hideshi Nishida , Takeshi Tanaka
IPC分类号： G06F9/302
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30058 , G06F9/30072 , G06F9/3885
摘要： An arithmetic processing apparatus capable of performing an arithmetic operation for generating a condition flag commonly referred to by using a condition flag generated on an arithmetic operation unit basis in as few steps as possible is provided. The arithmetic processing apparatus, which processes multiple data in parallel based on single instruction, includes: processing elements capable of performing a common arithmetic operation based on the evaluation result of the instruction stored in the instruction register; and a condition flag arithmetic operation unit capable of performing one of the logical operation and the comparison operation on the condition flag retained in each processing element, transferring the operation result to each processing element, and updating the condition flag based on the operation result.
摘要翻译：提供一种算术处理装置，其能够以尽可能少的步长进行用于生成通常使用在算术运算单元上生成的条件标志共同参照的条件标志的算术运算。基于单个指令并行处理多个数据的算术处理装置包括：能够基于存储在指令寄存器中的指令的评估结果执行公共算术运算的处理单元; 以及条件标志算术运算单元，其能够对保留在每个处理单元中的条件标志执行逻辑运算和比较运算中的一个，将运算结果传送给各处理单元，并根据运算结果更新条件标志。

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