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1. 发明授权

US5710770A ATM cell switching system 失效
公开(公告)号：US5710770A
公开(公告)日：1998-01-20
申请号：US462532
申请日：1995-06-05
申请人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki , Shinobu Gohara
发明人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki , Shinobu Gohara
IPC分类号： H04J3/24 , H04L12/56 , H04Q11/04
CPC分类号： H04L12/5601 , H04J3/247 , H04L12/5602 , H04L45/04 , H04L49/108 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/3081 , H04Q11/0478 , H04L2012/5627 , H04L2012/5631 , H04L2012/5638 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/568 , H04L2012/5681 , H04L2012/5682
摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

2. 再颁专利

USRE36751E ATM switching system connectable to I/O links having different transmission rates 失效
标题翻译： ATM交换系统可连接到具有不同传输速率的I / O链路
公开(公告)号：USRE36751E
公开(公告)日：2000-06-27
申请号：US430802
申请日：1995-04-26
申请人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki , Shinobu Gohara
发明人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki , Shinobu Gohara
IPC分类号： H04J3/24 , H04L12/56 , H04Q11/04
CPC分类号： H04Q11/0478 , H04J3/247 , H04L12/5601 , H04L12/5602 , H04L45/04 , H04L49/108 , H04L49/256 , H04L49/3081 , H04L2012/5627 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5681
摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.
摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元表装置。

3. 发明授权

US5799014A ATM cell switching system 失效
公开(公告)号：US5799014A
公开(公告)日：1998-08-25
申请号：US306978
申请日：1994-09-16
申请人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki , Shinobu Gohara
发明人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki , Shinobu Gohara
IPC分类号： H04J3/24 , H04L12/56 , H04Q11/04
CPC分类号： H04L12/5601 , H04J3/247 , H04L12/5602 , H04L45/04 , H04L49/108 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/3081 , H04Q11/0478 , H04L2012/5627 , H04L2012/5631 , H04L2012/5638 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/568 , H04L2012/5681 , H04L2012/5682
摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

4. 发明授权

US06330240B1 ATM cell switching system 失效
标题翻译： ATM信元交换系统
公开(公告)号：US06330240B1
公开(公告)日：2001-12-11
申请号：US09351125
申请日：1999-07-12
申请人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki
发明人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04J3/247 , H04L12/5602 , H04L45/04 , H04L49/108 , H04L49/203 , H04L49/255 , H04L2012/565 , H04L2012/5652 , H04L2012/5672 , H04L2012/5681 , H04Q11/0478
摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.
摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元表装置。

5. 发明授权

US5365519A ATM switch1ng system connectable to I/O links having different transmission rates 失效
标题翻译： ATM交换机可连接到具有不同传输速率的I / O链路
公开(公告)号：US5365519A
公开(公告)日：1994-11-15
申请号：US845668
申请日：1992-03-04
申请人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki
发明人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki
IPC分类号： H04J3/24 , H04L12/56 , H04Q11/04
CPC分类号： H04L12/5601 , H04J3/247 , H04L12/5602 , H04L45/04 , H04L49/108 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/3081 , H04Q11/0478 , H04L2012/5627 , H04L2012/5631 , H04L2012/5638 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/568 , H04L2012/5681 , H04L2012/5682
摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.
摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元表装置。

6. 发明授权

US06463057B1 ATM cell switching system 失效
标题翻译： ATM信元交换系统
公开(公告)号：US06463057B1
公开(公告)日：2002-10-08
申请号：US09714947
申请日：2000-11-20
申请人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki , Shinobu Gohara
发明人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki , Shinobu Gohara
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04J3/247 , H04L12/5602 , H04L45/04 , H04L49/108 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L2012/5627 , H04L2012/5631 , H04L2012/5638 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/568 , H04L2012/5681 , H04L2012/5682 , H04Q11/0478
摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.
摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元表装置。

7. 发明授权

US06396831B1 ATM cell switching system 失效
公开(公告)号：US06396831B1
公开(公告)日：2002-05-28
申请号：US09715104
申请日：2000-11-20
申请人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki , Shinobu Gohara
发明人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki , Shinobu Gohara
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04J3/247 , H04L12/5602 , H04L45/04 , H04L49/108 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L2012/5627 , H04L2012/5631 , H04L2012/5638 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/568 , H04L2012/5681 , H04L2012/5682 , H04Q11/0478
摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

8. 发明授权

US06339596B1 ATM cell switching system 失效
公开(公告)号：US06339596B1
公开(公告)日：2002-01-15
申请号：US08906909
申请日：1997-08-06
申请人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki , Shinobu Gohara
发明人： Takahiko Kozaki , Junichirou Yanagi , Kiyoshi Aiki , Yutaka Ito , Kaoru Aoki , Shinobu Gohara
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04J3/247 , H04L12/5602 , H04L45/04 , H04L49/108 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L2012/5627 , H04L2012/5631 , H04L2012/5638 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/568 , H04L2012/5681 , H04L2012/5682 , H04Q11/0478
摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

9. 发明授权

US6075767A Asynchronous transmission mode (ATM) handler 失效
标题翻译：异步传输模式（ATM）处理程序
公开(公告)号：US6075767A
公开(公告)日：2000-06-13
申请号：US820834
申请日：1997-03-19
申请人： Ken'ichi Sakamoto , Takahiko Kozaki , Junichirou Yanagi
发明人： Ken'ichi Sakamoto , Takahiko Kozaki , Junichirou Yanagi
IPC分类号： H04M3/22 , H04L12/70 , H04L12/711 , H04L12/951 , H04Q3/00 , H04Q11/04 , H04J1/16 , H04L12/28
CPC分类号： H04Q11/0478 , H04L2012/562 , H04L2012/5627
摘要： An ATM handler that sets a switchover indication to a control register according to a system switchover order from a controller such that a switchover indication is supplied to a selector and line interfaces according to an output signal from the register. The setting of a switchover indication synchronize a switchover of an operation to count user cells between the line interfaces of the active and standby systems with a switchover of a stream of input cells to an ATM switch by a selector. A protection period is provided to allow a time after the system switchover according to a transmission delay lag. The line interface related to a delayed phase assigns a bit for stopping counting to cells input during the protection period so that the counting operation is conducted for the cells other than those assigned with the bit for stopping counting. As a result, duplicate of counting cells is prevented and the number of user cells are accurately counted.
摘要翻译： ATM处理器，其根据来自控制器的系统切换顺序将切换指示设置为控制寄存器，使得切换指示根据来自寄存器的输出信号提供给选择器和线路接口。切换指示的设置使操作的切换同步主动和备用系统的线路接口之间的用户单元的计数，通过选择器将输入单元流切换到ATM交换机。提供保护期限，以便根据传输延迟滞后在系统切换后的时间。与延迟相位相关的线路接口在保护期间分配一个位用于停止计数到单元输入的位，以便对除了用于停止计数的位以外的单元进行计数操作。结果，防止了计数单元的重复，并且准确地计数了用户单元的数量。

10. 发明授权

US5280475A Traffic shaping method and circuit 失效
标题翻译：流量整形方法及电路
公开(公告)号：US5280475A
公开(公告)日：1994-01-18
申请号：US745466
申请日：1991-08-14
申请人： Junichirou Yanagi , Akihiko Takase , Takahiko Kozaki , Shinobu Gohara
发明人： Junichirou Yanagi , Akihiko Takase , Takahiko Kozaki , Shinobu Gohara
IPC分类号： H04Q3/00 , H04L12/815 , H04L12/863 , H04L12/931 , H04L12/951 , H04Q11/04 , H04L12/56
CPC分类号： H04L12/5601 , H04L12/5602 , H04L49/108 , H04L49/255 , H04L49/3081 , H04Q11/0478 , H04L2012/568
摘要： A traffic shaping method and circuit of a packet switching system in which input packets having a fixed length and multiplexed on a plurality of inputs are multiplexed to be delivered on any output of a plurality of outputs, connects the input packet to a list structure using an address chain formed for each output, forms the list structure even for each line identifier provided in the packet, and assigns the identifier for each time slot of the output to take out the packet from the list structure, to thereby prevent the packet having the same identifier from being multiplexed and delivering to the output continuously.
摘要翻译：一种分组交换系统的流量整形方法和电路，其中具有固定长度并在多个输入上复用的输入分组被多路复用以在多个输出的任何输出上传送，将输入分组连接到列表结构，使用为每个输出形成的地址链，甚至对于分组中提供的每个行标识符也形成列表结构，并且分配输出的每个时隙的标识符以从列表结构中取出分组，从而防止具有相同的分组标识符被多路复用并连续传送到输出。

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