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1. 发明授权

US4848022A Handle for a fishing rod 失效
标题翻译：处理钓鱼竿
公开(公告)号：US4848022A
公开(公告)日：1989-07-18
申请号：US275227
申请日：1988-11-22
申请人： Takafumi Ozeki , Kikuo Sakai , Noriyasu Fukushima
发明人： Takafumi Ozeki , Kikuo Sakai , Noriyasu Fukushima
IPC分类号： A01K97/08
CPC分类号： A01K97/08
摘要： The handle for a fishing rod according to the present invention can improve the sense of fit of the fingers with respect to a reel-attaching portion when said portion is taken hold of. The handle comprises a reel-depositing surface of the reel-attaching portion expanded in both right and left directions to form a bulgy portion which makes the width of said surface larger than that of a reel-foot. In accordance with the reel-depositing surface, the finger-placing surface of the reel-attaching portion is formed to have a large circular surface area which fits well with the dispositions and the bending angle of the fingers. This configulation is very advantageous in giving an improved sense of fit of the fingers with respect to the finger-placing surface of the reel-attaching portion and also a comfortable and safe gripping performance. Further, as the reel-attaching portion is formed thin enough for the lower surface of the outer periphery of the fishing rod to be exposed on the lower portion thereof, a firm and stable gripping performance can be obtained; and further the vibration of the rod can be sensed directly, so a user doesn't miss any chance to operate his rod and reel when fish hit and can have a better fishing result.
摘要翻译：根据本发明的钓竿手柄可以在保持所述部分时改善手指相对于卷轴安装部分的配合感。手柄包括卷轴安装部分的卷轴沉积表面，其在左右方向上扩展，以形成使得所述表面的宽度大于卷轴的宽度的凸起部分。根据卷轴沉积表面，卷轴安装部分的指状放置表面形成为具有与手指的配置和弯曲角度良好配合的大的圆形表面积。这种配置在提供手指相对于卷轴附接部分的手指放置表面的改进的配合感以及舒适和安全的抓握性能方面是非常有利的。此外，由于将钓竿外周的下表面形成为足够薄的卷轴安装部分露出在其下部，所以可以获得牢固和稳定的抓握性能; 并且进一步可以直接感测杆的振动，因此当鱼撞击并且可以具有更好的捕捞结果时，用户不会错过任何操作他的杆和卷轴的机会。

2. 发明授权

US4604749A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4604749A
公开(公告)日：1986-08-05
申请号：US502636
申请日：1983-06-09
申请人： Takashi Shinoda , Kikuo Sakai , Masahiro Ogata , Hiroshi Kawamoto , Yoshiaki Onishi, deceased , Junko Onishi, administratrix
发明人： Takashi Shinoda , Kikuo Sakai , Masahiro Ogata , Hiroshi Kawamoto , Yoshiaki Onishi, deceased , Junko Onishi, administratrix
IPC分类号： G06F11/10 , G11C17/08
CPC分类号： G06F11/1008 , G06F11/1076 , G11C17/08
摘要： YA semiconductor memory is provided with memory cells for storing a plurality of sets of data, each of the sets having check bits. A selecting circuit selects some of the memory cells to form a set in response to a first address signal. The circuit includes an error correcting code circuit, a tristate circuit and a control circuit which forms a control signal to control the tristate circuit. Output terminals of the tristate circuit are coupled with external output terminals of the semiconductor memory. Also, the tristate circuit is controlled by the control signal to bring the external circuit terminals into high impedance at least during the time when the error correcting code circuit is delivering indefinite data.
摘要翻译： YA半导体存储器设置有用于存储多组数据的存储单元，每组具有校验位。选择电路响应于第一地址信号选择一些存储器单元以形成集合。电路包括纠错码电路，三态电路和形成控制信号以控制三态电路的控制电路。三态电路的输出端子与半导体存储器的外部输出端子耦合。此外，三态电路由控制信号控制，至少在纠错码电路传送不定数据的时间内使外部电路端子变为高阻抗。

3. 发明授权

US5181983A Adhesive tape cutting device 失效
标题翻译：胶带切割装置
公开(公告)号：US5181983A
公开(公告)日：1993-01-26
申请号：US717493
申请日：1991-06-19
申请人： Kikuo Sakai
发明人： Kikuo Sakai
IPC分类号： B65H35/00
CPC分类号： B65H35/0033 , Y10T156/1348 , Y10T156/1793 , Y10T156/1795 , Y10T156/18 , Y10T225/22 , Y10T225/276
摘要： An adhesive tape cutting device rotatably supporting an adhesive tape roll, which is adapted to adhere an adhesive tape of a desired length on a surface of an object, and is capable of reliably and repeatedly delivering the next tip of the tape from the adhesive tape roll for the next adhesion operation. The device comprises a lever movably mounted on the base member; a pressing surface portion, which is formed on a bottom portion of the lever for pressing the upper surface of the adhesive tape at the time of adhering the tape; an arm member provided on a portion of the lever for temporarily fixing a delivered portion of the tape on a temporary fixing member mounted on the base member; and a blade mounted on the lever for cutting a free end portion of the tape. It is possible to perform operations of adhering and cutting by simply displacing the lever relative to a guiding edge formed on the bottom of the base member.

4. 发明授权

US4912674A Read-only memory 失效
标题翻译：只读存储器
公开(公告)号：US4912674A
公开(公告)日：1990-03-27
申请号：US310353
申请日：1989-02-14
申请人： Youichi Matsumoto , Ryuuji Shibata , Isamu Kobayashi , Satoshi Meguro , Kouichi Nagasawa , Hideo Meguro , Hisahiro Moriuchi , Masahiro Ogata , Kikuo Sakai , Toshifumi Takeda
发明人： Youichi Matsumoto , Ryuuji Shibata , Isamu Kobayashi , Satoshi Meguro , Kouichi Nagasawa , Hideo Meguro , Hisahiro Moriuchi , Masahiro Ogata , Kikuo Sakai , Toshifumi Takeda
IPC分类号： G11C17/12 , H01L27/112
CPC分类号： H01L27/112 , G11C17/126
摘要： A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.
摘要翻译：掩模编程的ROM包括在存储器阵列中的数据线和电源电压之间提供的耗尽型负载MOSFET，MOSFET具有施加到其栅极的电路的接地电位。数据的读取由放大MOSFET进行，该放大MOSFET通过在其栅极处提供电路接地电位的耗尽型MOSFET向所选择的数据线提供电流。因此，分别施加到数据线的偏置电压和接收从所选择的数据线读出的信号的读出放大器彼此相等，从而实现高速读取操作。

5. 发明授权

US4780875A Semiconductor memory with reduced size ECC circuit 失效
标题翻译：半导体存储器缩小ECC电路
公开(公告)号：US4780875A
公开(公告)日：1988-10-25
申请号：US893772
申请日：1986-08-06
申请人： Kikuo Sakai
发明人： Kikuo Sakai
IPC分类号： G06F12/16 , G06F11/10 , G11C29/00 , G11C29/42
CPC分类号： G06F11/1008 , G06F11/1076
摘要： A semiconductor memory incorporating an ECC circuit includes a memory array, means for selecting a plurality of bits which are to be simultaneously output to the outside of the IC from a plurality of bits which are simultaneously read out from the memory array, and an error correcting circuit which constitutes the ECC circuit. The selecting means is provided in a stage previous to the error correcting circuit. In consequence, it is possible to reduce the number of bits of a signal which need to be simultaneously processed by the error correcting circuit. Accordingly, the size of the ECC circuit can be reduced.
摘要翻译：包含ECC电路的半导体存储器包括存储器阵列，用于从同时从存储器阵列读出的多个位选择要同时输出到IC外部的多个位的装置和纠错构成ECC电路的电路。选择装置设置在纠错电路之前的阶段。因此，可以减少由纠错电路需要同时处理的信号的位数。因此，可以减小ECC电路的尺寸。

6. 发明授权

US4839860A Semiconductor device having head only memory with differential amplifier 失效
标题翻译：半导体器件具有仅具有差分放大器的头部存储器
公开(公告)号：US4839860A
公开(公告)日：1989-06-13
申请号：US820523
申请日：1986-01-17
申请人： Takashi Shinoda , Kikuo Sakai , Masahiro Ogata , Hiroshi Kawamoto , Yoshiaki Onishi, deceased , by Junko Onishi, administratrix
发明人： Takashi Shinoda , Kikuo Sakai , Masahiro Ogata , Hiroshi Kawamoto , Yoshiaki Onishi, deceased , by Junko Onishi, administratrix
IPC分类号： G06F11/10 , G11C17/08
CPC分类号： G06F11/1008 , G06F11/1076 , G11C17/08
摘要： A semiconductor memory includes a dummy cell for forming a reference potential, a read-only memory cell, and a differential amplifier circuit which receives the reference potential formed by the dummy cell and a signal read out from the memory cell. The differential amplifier circuit is dynamically operated so that the semiconductor memory is made smaller in power consumption and size than conventional units. Moreover, in order to reduce the power consumption, the memory cell is brought into the nonselection state when a predetermined time has passed after being selected. In addition, the semiconductor memory is provided with a compensating circuit in order to make the value of the capacitance connected to a word line for transmitting a selecting signal to the memory cell and the value of the capacitance connected to a dummy word line for transmitting a selecting signal to the dummy cell substantially equal to each other. Thus, the changes in potential of both the selecting signals are made substantially equal to each other. Accordingly, it is possible to reduce malfunctions.
摘要翻译：半导体存储器包括用于形成参考电位的虚拟单元，只读存储单元和接收由虚设单元形成的参考电位的差分放大器电路和从存储单元读出的信号。差分放大器电路是动态操作的，使得半导体存储器的功耗和尺寸比常规单元小。此外，为了降低功耗，当选择了规定时间后，使存储单元变为非选择状态。此外，半导体存储器设置有补偿电路，以便连接到用于将选择信号发送到存储单元的字线的电容的值和连接到用于发送选择信号的虚拟字线的电容的值选择到虚拟单元的信号基本相等。因此，使选择信号的电位变化大致相等。因此，可以减少故障。

7. 发明授权

US4805143A Read-only memory 失效
标题翻译：只读存储器
公开(公告)号：US4805143A
公开(公告)日：1989-02-14
申请号：US2291
申请日：1987-01-12
申请人： Youichi Matsumoto , Ryuuji Shibata , Isamu Kobayashi , Satoshi Meguro , Kouichi Nagasawa , Hideo Meguro , Hisahiro Moriuchi , Masahiro Ogata , Kikuo Sakai , Toshifumi Takeda
发明人： Youichi Matsumoto , Ryuuji Shibata , Isamu Kobayashi , Satoshi Meguro , Kouichi Nagasawa , Hideo Meguro , Hisahiro Moriuchi , Masahiro Ogata , Kikuo Sakai , Toshifumi Takeda
IPC分类号： G11C17/12 , H01L27/112 , G11C17/00
CPC分类号： H01L27/112 , G11C17/126
摘要： A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.
摘要翻译：掩模编程的ROM包括在存储器阵列中的数据线和电源电压之间提供的耗尽型负载MOSFET，MOSFET具有施加到其栅极的电路的接地电位。数据的读取由放大MOSFET进行，该放大MOSFET通过在其栅极处提供电路接地电位的耗尽型MOSFET向所选择的数据线提供电流。因此，分别施加到数据线的偏置电压和接收从所选择的数据线读出的信号的读出放大器彼此相等，从而实现高速读取操作。

8. 发明授权

US4592024A Semiconductor ROM 失效
标题翻译：半导体ROM
公开(公告)号：US4592024A
公开(公告)日：1986-05-27
申请号：US510319
申请日：1983-07-01
申请人： Kikuo Sakai , Yoshiaki Onishi, deceased , by Junko Onishi, administratrix
发明人： Kikuo Sakai , Yoshiaki Onishi, deceased , by Junko Onishi, administratrix
IPC分类号： G06F12/16 , G06F11/14 , G11C29/00 , H01L27/10 , G11C7/00
CPC分类号： G11C29/70 , G06F11/14
摘要： The address of each defective memory cell in a memory cell array is stored within a semiconductor ROM in advance. In parallel with the operation of reading out information from a memory cell of the array, whether or not the address of the memory cell agrees with the previously stored address of a defective memory cell is distinguished. When they agree, a correcting signal is formed. Erroneous data read out from the defective memory cell is inverted on the basis of the correcting signal and thus corrected, whereupon the corrected data is delivered out of the ROM. In using this error data correcting system, a read-out access time delay caused by furnishing the correcting function corresponds to only one stage of a logic circuit which is used for the inversion to correct the erroneous data. Thus, a semiconductor ROM furnished with an error correcting function can be provided without spoiling enhancement in the speed of the read-out operation.
摘要翻译：存储单元阵列中的每个有缺陷的存储单元的地址预先存储在半导体ROM内。与从阵列的存储单元读出信息的操作并行地，区分存储器单元的地址是否与先前存储的有缺陷的存储器单元的地址一致。当它们同意时，形成校正信号。根据校正信号反转从缺陷存储单元读出的错误数据，由此校正，校正后的数据从ROM中传送出去。在使用该误差数据校正系统时，通过提供校正功能引起的读出访问时间延迟仅对应于用于反转的逻辑电路的一个阶段来校正错误数据。因此，可以提供具有纠错功能的半导体ROM，而不会破坏读出操作的速度。

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