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1. 发明授权

US08120118B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08120118B2
公开(公告)日：2012-02-21
申请号：US12943600
申请日：2010-11-10
申请人： Shinsuke Sakashita , Takaaki Kawahara , Jiro Yugami
发明人： Shinsuke Sakashita , Takaaki Kawahara , Jiro Yugami
IPC分类号： H01L21/70
CPC分类号： H01L21/823842
摘要： Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing.
摘要翻译：提供一种高度可靠的半导体器件，其分别配备有具有期望特性的多个半导体元件; 以及便于制造半导体器件的制造方法。半导体器件通过在栅极绝缘膜的整个上表面上形成厚度为3至30nm的栅电极金属膜来制造; 通过使用与栅电极金属膜不同的材料，在属于nFET区域的栅极金属膜的一部分的整个上表面上形成厚度为10nm以下的n侧覆盖层; 在n侧盖层上进行热处理，将n侧盖层的材料向n侧盖层正下方的栅电极金属膜扩散，形成n侧栅电极金属膜在nFET区域。然后沉积多晶硅层，随后进行栅电极处理。

2. 发明申请

US20080121999A1 SEMICONDUCTOR DEVICE WHICH HAS MOS STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有MOS结构的半导体器件及其制造方法
公开(公告)号：US20080121999A1
公开(公告)日：2008-05-29
申请号：US11772624
申请日：2007-07-02
申请人： Takaaki KAWAHARA , Shinsuke Sakashita , Jiro Yugami
发明人： Takaaki KAWAHARA , Shinsuke Sakashita , Jiro Yugami
IPC分类号： H01L29/78 , H01L21/04
CPC分类号： H01L21/82345 , H01L21/823842 , H01L27/088 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/7833
摘要： The present invention offers the semiconductor device which can solve each problem, such as Fermi level pinning, formation of gate electrode depletion, and a diffusion phenomenon, can adopt a material suitable for each gate electrode of the MOS structure from which threshold voltage differs, and can adjust (control) threshold voltage appropriately by the manufacturing process simplified more and which has a MOS structure.In the semiconductor device which has a MOS structure concerning the present invention, a PMOS transistor has the structure in which the gate insulating film, first metal layer, second metal layer, and polysilicon layer was formed in the order concerned. An NMOS transistor has the structure by which a gate insulating film and polysilicon were formed in the order concerned.
摘要翻译：本发明提供了能够解决诸如费米能级钉扎，栅电极耗尽的形成和扩散现象等各种问题的半导体器件，可以采用适合阈值电压不同的MOS结构的每个栅电极的材料，以及可以通过制造工艺适当地调整（控制）阈值电压，并且具有MOS结构。在具有本发明的MOS结构的半导体器件中，PMOS晶体管具有以相关顺序形成栅极绝缘膜，第一金属层，第二金属层和多晶硅层的结构。 NMOS晶体管具有以相关顺序形成栅极绝缘膜和多晶硅的结构。

3. 发明授权

US08293632B2 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US08293632B2
公开(公告)日：2012-10-23
申请号：US12755058
申请日：2010-04-06
申请人： Masaru Kadoshima , Shinsuke Sakashita , Takaaki Kawahara , Jiro Yugami
发明人： Masaru Kadoshima , Shinsuke Sakashita , Takaaki Kawahara , Jiro Yugami
IPC分类号： H01L21/3205
CPC分类号： H01L21/823857
摘要： To improve productivity and performance of a CMISFET including a high-dielectric-constant gate insulating film and a metal gate electrode. An Hf-containing insulating film for a gate insulating film is formed over the main surface of a semiconductor substrate. A metal nitride film is formed on the insulating film. The metal nitride film in an nMIS formation region where an n-channel MISFET is to be formed is selectively removed by wet etching using a photoresist pattern on the metal nitride films a mask. Then, a threshold adjustment film containing a rare-earth element is formed. The Hf-containing insulating film in the nMIS formation region reacts with the threshold adjustment film by heat treatment. The Hf-containing insulating film in a pMIS formation region where a p-channel MISFET is to be formed does not react with the threshold adjustment film because of the existence of the metal nitride film. Then, after removing the unreacted threshold adjustment film and the metal nitride film, metal gate electrodes are formed in the nMIS formation region and the pMIS formation region.
摘要翻译：提高包括高介电常数栅极绝缘膜和金属栅电极在内的CMISFET的生产率和性能。在半导体衬底的主表面上形成用于栅极绝缘膜的含Hf绝缘膜。在绝缘膜上形成金属氮化物膜。通过在金属氮化物膜上使用光刻胶图案的掩模，通过湿式蚀刻选择性地去除要形成n沟道MISFET的nMIS形成区域中的金属氮化物膜。然后，形成含有稀土元素的阈值调节膜。 nMIS形成区域中的含Hf绝缘膜通过热处理与阈值调节膜反应。由于存在金属氮化物膜，所以要形成p沟道MISFET的pMIS形成区域中的含Hf绝缘膜不会与阈值调节膜反应。然后，在除去未反应的阈值调整膜和金属氮化物膜之后，在nMIS形成区域和pMIS形成区域中形成金属栅电极。

4. 发明授权

US07855134B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07855134B2
公开(公告)日：2010-12-21
申请号：US12354434
申请日：2009-01-15
申请人： Shinsuke Sakashita , Takaaki Kawahara , Jiro Yugami
发明人： Shinsuke Sakashita , Takaaki Kawahara , Jiro Yugami
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842
摘要： Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing.
摘要翻译：提供一种高度可靠的半导体器件，其分别配备有具有期望特性的多个半导体元件; 以及便于制造半导体器件的制造方法。半导体器件通过在栅极绝缘膜的整个上表面上形成厚度为3至30nm的栅电极金属膜来制造; 通过使用与栅电极金属膜不同的材料，在属于nFET区域的栅极金属膜的一部分的整个上表面上形成厚度为10nm以下的n侧覆盖层; 在n侧盖层上进行热处理，将n侧盖层的材料向n侧盖层正下方的栅电极金属膜扩散，形成n侧栅电极金属膜在nFET区域。然后沉积多晶硅层，随后进行栅电极处理。

5. 发明申请

US20090218634A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090218634A1
公开(公告)日：2009-09-03
申请号：US12354434
申请日：2009-01-15
申请人： Shinsuke Sakashita , Takaaki Kawahara , Jiro Yugami
发明人： Shinsuke Sakashita , Takaaki Kawahara , Jiro Yugami
IPC分类号： H01L27/092 , H01L21/3205
CPC分类号： H01L21/823842
摘要： Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing.
摘要翻译：提供一种高度可靠的半导体器件，其分别配备有具有期望特性的多个半导体元件; 以及便于制造半导体器件的制造方法。半导体器件通过在栅极绝缘膜的整个上表面上形成厚度为3至30nm的栅电极金属膜来制造; 通过使用与栅电极金属膜不同的材料，在属于nFET区域的栅极金属膜的一部分的整个上表面上形成厚度为10nm以下的n侧覆盖层; 在n侧盖层上进行热处理，将n侧盖层的材料向n侧盖层正下方的栅电极金属膜扩散，形成n侧栅电极金属膜在nFET区域。然后沉积多晶硅层，随后进行栅电极处理。

6. 发明申请

US20100279496A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20100279496A1
公开(公告)日：2010-11-04
申请号：US12755058
申请日：2010-04-06
申请人： Masaru KADOSHIMA , Shinsuke Sakashita , Takaaki Kawahara , Jiro Yugami
发明人： Masaru KADOSHIMA , Shinsuke Sakashita , Takaaki Kawahara , Jiro Yugami
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： To improve productivity and performance of a CMISFET including a high-dielectric-constant gate insulating film and a metal gate electrode. An Hf-containing insulating film for a gate insulating film is formed over the main surface of a semiconductor substrate. A metal nitride film is formed on the insulating film. The metal nitride film in an nMIS formation region where an n-channel MISFET is to be formed is selectively removed by wet etching using a photoresist pattern on the metal nitride films a mask. Then, a threshold adjustment film containing a rare-earth element is formed. The Hf-containing insulating film in the nMIS formation region reacts with the threshold adjustment film by heat treatment. The Hf-containing insulating film in a pMIS formation region where a p-channel MISFET is to be formed does not react with the threshold adjustment film because of the existence of the metal nitride film. Then, after removing the unreacted threshold adjustment film and the metal nitride film, metal gate electrodes are formed in the nMIS formation region and the pMIS formation region.
摘要翻译：提高包括高介电常数栅极绝缘膜和金属栅电极在内的CMISFET的生产率和性能。在半导体衬底的主表面上形成用于栅极绝缘膜的含Hf绝缘膜。在绝缘膜上形成金属氮化物膜。通过在金属氮化物膜上使用光刻胶图案的掩模，通过湿式蚀刻选择性地去除要形成n沟道MISFET的nMIS形成区域中的金属氮化物膜。然后，形成含有稀土元素的阈值调节膜。 nMIS形成区域中的含Hf绝缘膜通过热处理与阈值调节膜反应。由于存在金属氮化物膜，所以要形成p沟道MISFET的pMIS形成区域中的含Hf绝缘膜不会与阈值调节膜反应。然后，在除去未反应的阈值调整膜和金属氮化物膜之后，在nMIS形成区域和pMIS形成区域中形成金属栅电极。

7. 发明授权

US07741201B2 Semiconductor device and method of manufacturing a gate stack 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07741201B2
公开(公告)日：2010-06-22
申请号：US11371082
申请日：2006-03-09
申请人： Jiro Yugami , Masao Inoue , Kenichi Mori , Shinsuke Sakashita
发明人： Jiro Yugami , Masao Inoue , Kenichi Mori , Shinsuke Sakashita
IPC分类号： H01L21/3205
CPC分类号： H01L29/495 , H01L21/28176 , H01L29/4966 , H01L29/517 , H01L29/66575
摘要： The semiconductor device includes a semiconductor substrate, a gate insulating film formed in contact with an upper side of the semiconductor substrate, and a gate electrode formed on the upper side of the gate insulating film and made of metal nitride or metal nitride silicide. A buffer layer for preventing diffusion of nitrogen and silicon is interposed between the gate insulating film and the gate electrode. Preferably, the buffer layer has a thickness of 5 nm or less. In the case where gate electrode contains Ti elements, and the gate insulating film contains Hf elements, the buffer layer preferably contains a titanium film.
摘要翻译：半导体器件包括半导体衬底，与半导体衬底的上侧接触形成的栅极绝缘膜，以及形成在栅极绝缘膜的上侧并由金属氮化物或金属氮化物硅化物制成的栅电极。用于防止氮和硅扩散的缓冲层插入在栅极绝缘膜和栅电极之间。优选地，缓冲层的厚度为5nm以下。在栅极含有Ti元素，栅极绝缘膜含有Hf元素的情况下，缓冲层优选含有钛膜。

8. 发明申请

US20060214245A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060214245A1
公开(公告)日：2006-09-28
申请号：US11371082
申请日：2006-03-09
申请人： Jiro Yugami , Masao Inoue , Kenichi Mori , Shinsuke Sakashita
发明人： Jiro Yugami , Masao Inoue , Kenichi Mori , Shinsuke Sakashita
IPC分类号： H01L29/94
CPC分类号： H01L29/495 , H01L21/28176 , H01L29/4966 , H01L29/517 , H01L29/66575
摘要： The semiconductor device includes a semiconductor substrate, a gate insulating film formed in contact with an upper side of the semiconductor substrate, and a gate electrode formed on the upper side of the gate insulating film and made of metal nitride or metal nitride silicide. A buffer layer for preventing diffusion of nitrogen and silicon is interposed between the gate insulating film and the gate electrode. Preferably, the buffer layer has a thickness of 5 nm or less. In the case where gate electrode contains Ti elements, and the gate insulating film contains Hf elements, the buffer layer preferably contains a titanium film.
摘要翻译：半导体器件包括半导体衬底，与半导体衬底的上侧接触形成的栅极绝缘膜，以及形成在栅极绝缘膜的上侧并由金属氮化物或金属氮化物硅化物制成的栅电极。用于防止氮和硅扩散的缓冲层插入在栅极绝缘膜和栅电极之间。优选地，缓冲层的厚度为5nm以下。在栅极含有Ti元素，栅极绝缘膜含有Hf元素的情况下，缓冲层优选含有钛膜。

9. 发明申请

US20120045876A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20120045876A1
公开(公告)日：2012-02-23
申请号：US13183996
申请日：2011-07-15
申请人： Takaaki KAWAHARA , Shinsuke Sakashita , Masaru Kadoshima , Hiroshi Umeda
发明人： Takaaki KAWAHARA , Shinsuke Sakashita , Masaru Kadoshima , Hiroshi Umeda
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： There is provided a technology capable of preventing the increase in threshold voltages of n channel type MISFETs and p channel type MISFETs in a semiconductor device including CMISFETs having high dielectric constant gate insulation films and metal gate electrodes. When a rare earth element or aluminum is introduced into a Hf-containing insulation film which is a high dielectric constant gate insulation film for the purpose of adjusting the threshold value of the CMISFET, a threshold adjustment layer including a lanthanum film scarcely containing oxygen, and a threshold adjustment layer including an aluminum film scarcely containing oxygen are formed over the Hf-containing insulation film in an nMIS formation region and a pMIS formation region, respectively. This prevents oxygen from being diffused from the threshold adjustment layers into the Hf-containing insulation film and the main surface of a semiconductor substrate.
摘要翻译：提供了能够防止包括具有高介电常数栅极绝缘膜和金属栅电极的CMISFET的半导体器件中的n沟道型MISFET和p沟道型MISFET的阈值电压增加的技术。当为了调整CMISFET的阈值而将稀土元素或铝引入到作为高介电常数栅极绝缘膜的Hf的绝缘膜中时，包括几乎不含有氧的镧膜的阈值调整层和在nMIS形成区域和pMIS形成区域中分别在Hf的绝缘膜上形成包含几乎不含氧的铝膜的阈值调整层。这防止氧从阈值调节层扩散到含Hf的绝缘膜和半导体衬底的主表面。

10. 发明申请

US20100320542A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100320542A1
公开(公告)日：2010-12-23
申请号：US12782457
申请日：2010-05-18
申请人： Takaaki Kawahara , Shinsuke Sakashita , Masaru Kadoshima
发明人： Takaaki Kawahara , Shinsuke Sakashita , Masaru Kadoshima
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823857 , H01L27/092
摘要： To improve the performance of a CMISFET having a high-k gate insulating film and a metal gate electrode. An n-channel MISFET has, over the surface of a p-type well of a semiconductor substrate, a gate electrode formed via a first Hf-containing insulating film serving as a gate insulating film, while a p-channel MISFET has, over the surface of an n-type well, another gate electrode formed via a second Hf-containing insulating film serving as a gate insulating film. These gate electrodes have a stack structure of a metal film and a silicon film thereover. The first Hf-containing insulating film is an insulating material film comprised of Hf, a rare earth element, Si, O, and N or comprised of Hf, a rare earth element, Si, and O, while the second Hf-containing insulating film is an insulating material film comprised of Hf, Al, O, and N or comprised of Hf, Al, and O.
摘要翻译：为了提高具有高k栅极绝缘膜和金属栅电极的CMISFET的性能。 n沟道MISFET在半导体衬底的p型阱的表面上具有通过用作栅极绝缘膜的第一Hf绝缘膜形成的栅电极，而p沟道MISFET具有 n型阱的表面，通过用作栅极绝缘膜的第二Hf含量绝缘膜形成的另一个栅电极。这些栅电极具有金属膜和其上的硅膜的堆叠结构。第一含Hf绝缘膜是包括Hf，稀土元素，Si，O和N或由Hf，稀土元素，Si和O构成的绝缘材料膜，而第二Hf含量绝缘膜是由Hf，Al，O和N组成或由Hf，Al和O构成的绝缘材料膜。

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