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1. 发明申请

US20180342291A1 Read Margin Tracking In Memory Applications 审中-公开
公开(公告)号：US20180342291A1
公开(公告)日：2018-11-29
申请号：US15860782
申请日：2018-01-03
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hao-I Yang , Tsung-Hsien Huang
IPC分类号： G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C11/418
摘要： A sense amplify enable (SAE) signal is generated on a SAE line by receiving a trigger signal at a first circuit portion coupled to a first domain power supply and a second circuit portion coupled to a second domain power supply. The second domain power supply is separate and distinct from the first domain power supply. The first circuit portion and the second circuit portion are each further coupled to the SAE line for carrying the SAE signal. For a first period of time, a first portion of the SAE signal is generated based on the first domain power supply using the first circuit portion. And, for second period of time, a second portion of the SAE signal is generated based on the second domain power supply using a second circuit portion.

2. 发明授权

US09934845B2 Latch with built-in level shifter 有权
公开(公告)号：US09934845B2
公开(公告)日：2018-04-03
申请号：US15405423
申请日：2017-01-13
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Hao-I Yang , Cheng Hung Lee , Chi-Kai Hsieh , Fu-An Wu , Tsung-Hsien Huang
IPC分类号： G11C7/10 , G11C11/419 , H03K3/356 , H03K19/0175
CPC分类号： G11C11/419 , G11C7/10 , G11C7/1057 , G11C7/1084 , H03K3/356113 , H03K3/356139 , H03K3/356156 , H03K3/356191 , H03K19/0175
摘要： A semiconductor device comprising a first supply voltage, a second supply voltage, different from the first supply voltage; and a switching circuit. The switching circuit comprises an input configured to receive an input signal corresponding to the first supply voltage and an output configured to output an output signal corresponding to the second supply voltage. The switching circuit is a combined latch with a built-in level shifter that provides latching functionality and level shifting functionality and a leakage path is cut-off when the switching circuit is providing latching functionality.

3. 发明授权

US08958237B1 Static random access memory timing tracking circuit 有权
标题翻译：静态随机存取时序跟踪电路
公开(公告)号：US08958237B1
公开(公告)日：2015-02-17
申请号：US14078895
申请日：2013-11-13
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Hao-I Yang , Yi-Tzu Chen , Cheng-Jen Chang , Geng-Cing Lin , Yu-Hao Hu , Chia-Hao Hsu
IPC分类号： G11C11/40 , G11C11/419
CPC分类号： G11C11/419 , G11C7/14 , G11C8/08
摘要： An apparatus and method for executing a write operation in a static random access memory (SRAM) array including memory cells that are coupled to a plurality of word lines and to a plurality of bit lines are provided. A clock signal is generated to start a write operation. A pulse is generated on the plurality of word lines in response to the clock signal. An operation voltage of the SRAM array is lowered for a period of time during the write operation. The period of time is controlled and the pulse is ended using a tracking circuit. The tracking circuit includes a plurality of tracking memory cells. The plurality of tracking memory cells have a timing characteristic that emulates a timing characteristic of the SRAM array during the write operation. The tracking circuit controls the period of time and ends the pulse based on the emulated timing characteristic.
摘要翻译：提供了一种用于在包括耦合到多个字线和多个位线的存储器单元的静态随机存取存储器（SRAM）阵列中执行写入操作的装置和方法。生成时钟信号以开始写入操作。响应于时钟信号在多个字线上产生脉冲。在写入操作期间SRAM阵列的工作电压下降一段时间。该时间段被控制并且使用跟踪电路使脉冲结束。跟踪电路包括多个跟踪存储单元。多个跟踪存储单元具有在写入操作期间仿真SRAM阵列的定时特性的定时特性。跟踪电路根据仿真时序特性控制时间段并结束脉冲。

4. 发明授权

US10276232B2 Read margin tracking in memory applications 有权
公开(公告)号：US10276232B2
公开(公告)日：2019-04-30
申请号：US15860782
申请日：2018-01-03
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hao-I Yang , Tsung-Hsien Huang
IPC分类号： G11C11/00 , G11C11/419 , G11C11/418 , G11C7/08 , G11C5/14
摘要： A sense amplify enable (SAE) signal is generated on a SAE line by receiving a trigger signal at a first circuit portion coupled to a first domain power supply and a second circuit portion coupled to a second domain power supply. The second domain power supply is separate and distinct from the first domain power supply. The first circuit portion and the second circuit portion are each further coupled to the SAE line for carrying the SAE signal. For a first period of time, a first portion of the SAE signal is generated based on the first domain power supply using the first circuit portion. And, for second period of time, a second portion of the SAE signal is generated based on the second domain power supply using a second circuit portion.

5. 发明申请

US20170345487A1 Latch With Built-In Level Shifter 有权
公开(公告)号：US20170345487A1
公开(公告)日：2017-11-30
申请号：US15405423
申请日：2017-01-13
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Hao-I Yang , Cheng Hung Lee , Chi-Kai Hsieh , Fu-An Wu , Tsung-Hsien Huang
IPC分类号： G11C11/419 , H03K3/356
CPC分类号： G11C11/419 , G11C7/10 , G11C7/1057 , G11C7/1084 , H03K3/356113 , H03K3/356139 , H03K3/356156 , H03K3/356191 , H03K19/0175
摘要： A semiconductor device comprising a first supply voltage, a second supply voltage, different from the first supply voltage; and a switching circuit. The switching circuit comprises an input configured to receive an input signal corresponding to the first supply voltage and an output configured to output an output signal corresponding to the second supply voltage. The switching circuit is a combined latch with a built-in level shifter that provides latching functionality and level shifting functionality and a leakage path is cut-off when the switching circuit is providing latching functionality.

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