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1. 发明申请

US20180342291A1 Read Margin Tracking In Memory Applications 审中-公开
公开(公告)号：US20180342291A1
公开(公告)日：2018-11-29
申请号：US15860782
申请日：2018-01-03
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hao-I Yang , Tsung-Hsien Huang
IPC分类号： G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C11/418
摘要： A sense amplify enable (SAE) signal is generated on a SAE line by receiving a trigger signal at a first circuit portion coupled to a first domain power supply and a second circuit portion coupled to a second domain power supply. The second domain power supply is separate and distinct from the first domain power supply. The first circuit portion and the second circuit portion are each further coupled to the SAE line for carrying the SAE signal. For a first period of time, a first portion of the SAE signal is generated based on the first domain power supply using the first circuit portion. And, for second period of time, a second portion of the SAE signal is generated based on the second domain power supply using a second circuit portion.

2. 发明授权

US08988949B2 Header circuit for controlling supply voltage of a cell 有权
标题翻译：用于控制电池电源电压的标题电路
公开(公告)号：US08988949B2
公开(公告)日：2015-03-24
申请号：US13633222
申请日：2012-10-02
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Chung-Hsien Hua , Chung-Yi Wu , Chen-Lin Yang , Cheng Hung Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/417
摘要： One or more techniques or systems for controlling a supply voltage of a cell are provided herein. Additionally, one or more techniques or systems for mitigating leakage of the cell are provided. In some embodiments, a header circuit is provided, including a first pull-up p-type metal-oxide-semiconductor (PMOS) transistor including a first gate, a first source, and a first drain. Additionally, the header circuit includes a second pull-down PMOS transistor including a second gate, a second source, and a second drain. In some embodiments, the first drain of the first pull-up PMOS transistor is connected to the second source of the second pull-down PMOS transistor and a supply voltage line for one or more cells. In this manner, a pull-down PMOS is configured to control the supply voltage of the cell, thus facilitating voltage control for a write assist, for example.
摘要翻译：本文提供了用于控制电池的电源电压的一种或多种技术或系统。另外，提供了用于减轻电池泄漏的一种或多种技术或系统。在一些实施例中，提供了一种头部电路，包括包括第一栅极，第一源极和第一漏极的第一上拉p型金属氧化物半导体（PMOS）晶体管。另外，标题电路包括包括第二栅极，第二源极和第二漏极的第二下拉PMOS晶体管。在一些实施例中，第一上拉PMOS晶体管的第一漏极连接到第二下拉PMOS晶体管的第二源极和一个或多个单元的电源电压线。以这种方式，下拉PMOS被配置为控制电池的电源电压，从而便于例如用于写入辅助的电压控制。

3. 发明授权

US10276232B2 Read margin tracking in memory applications 有权
公开(公告)号：US10276232B2
公开(公告)日：2019-04-30
申请号：US15860782
申请日：2018-01-03
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hao-I Yang , Tsung-Hsien Huang
IPC分类号： G11C11/00 , G11C11/419 , G11C11/418 , G11C7/08 , G11C5/14
摘要： A sense amplify enable (SAE) signal is generated on a SAE line by receiving a trigger signal at a first circuit portion coupled to a first domain power supply and a second circuit portion coupled to a second domain power supply. The second domain power supply is separate and distinct from the first domain power supply. The first circuit portion and the second circuit portion are each further coupled to the SAE line for carrying the SAE signal. For a first period of time, a first portion of the SAE signal is generated based on the first domain power supply using the first circuit portion. And, for second period of time, a second portion of the SAE signal is generated based on the second domain power supply using a second circuit portion.

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