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1. 发明授权

US10276584B2 Method to control the common drain of a pair of control gates and to improve inter-layer dielectric (ILD) filling between the control gates 有权
公开(公告)号：US10276584B2
公开(公告)日：2019-04-30
申请号：US15408994
申请日：2017-01-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chung-Chiang Min , Tsung-Hsueh Yang , Chang-Ming Wu , Shih-Chang Liu
IPC分类号： H01L21/28 , H01L29/08 , H01L29/66 , H01L21/033 , H01L21/265 , H01L21/311 , H01L21/321 , H01L21/768 , H01L29/423 , H01L29/792 , H01L21/3105 , H01L21/3213 , H01L27/11568
摘要： A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

2. 发明申请

US20190067559A1 TOP ELECTRODE CAP STRUCTURE FOR EMBEDDED MEMORY 审中-公开
公开(公告)号：US20190067559A1
公开(公告)日：2019-02-28
申请号：US15687976
申请日：2017-08-28
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yao-Wen Chang , Tsung-Hsueh Yang
IPC分类号： H01L43/02 , H01L43/08 , H01L43/12
摘要： The present application relates to a method for forming a top-electrode cap structure on a memory cell. In some embodiments, a method for forming a top-electrode cap structure on a memory cell. The method includes providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes. An etch is performed into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell. A getter layer is then formed to line the via opening, and further, over and abutting the top electrode of the memory cell. An oxygen-resistant layer is formed over and abutting the getter layer.

3. 发明申请

US20160087056A1 SPLIT GATE MEMORY DEVICE FOR IMPROVED ERASE SPEED 有权
标题翻译：用于改进擦除速度的分离式闸门存储装置
公开(公告)号：US20160087056A1
公开(公告)日：2016-03-24
申请号：US14493538
申请日：2014-09-23
申请人： Taiwan Semiconductor Manufacturing co., Ltd.
发明人： Chang-Ming Wu , Tsung-Hsueh Yang , Sheng-Chieh Chen , Shih-Chang Liu
IPC分类号： H01L29/423 , H01L27/115 , H01L21/28 , H01L29/788
CPC分类号： H01L29/42328 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/788 , H01L29/7881
摘要： Some embodiments relate to a memory device with an asymmetric floating gate geometry. A control gate is arranged over a floating gate. An erase gate is arranged laterally adjacent the floating gate, and is separated from the floating gate by a tunneling dielectric layer. A sidewall spacer is arranged along a vertical sidewall of the control gate, and over an upper surface of the floating gate. A portion of the floating gate upper surface forms a “ledge,” or a sharp corner, which extends horizontally past the sidewall spacer. A sidewall of the floating gate forms a concave surface, which tapers down from the ledge towards a neck region within the floating gate. The ledge provides a faster path for tunneling of the electrons through the tunneling dielectric layer compared to a floating gate with a planar sidewall surface. The ledge consequently improves the erase speed of the memory device.
摘要翻译：一些实施例涉及具有不对称浮动门几何形状的存储器件。控制门布置在浮动门上。擦除栅极横向布置在浮动栅极附近，并且通过隧道电介质层与浮动栅极分离。侧壁间隔件沿着控制栅极的垂直侧壁并且在浮动栅极的上表面上方布置。浮动门上表面的一部分形成水平延伸通过侧壁间隔物的“凸缘”或尖角。浮动栅极的侧壁形成凹入表面，其从凸缘向下朝向浮动门内的颈部区域逐渐变细。与具有平面侧壁表面的浮动栅极相比，该凸缘提供了更快的隧道隧道隧穿隧道介电层的路径。因此，该凸起因此提高了存储器件的擦除速度。

4. 发明申请

US20190245138A1 TOP ELECTRODE CAP STRUCTURE FOR EMBEDDED MEMORY 审中-公开
公开(公告)号：US20190245138A1
公开(公告)日：2019-08-08
申请号：US16385271
申请日：2019-04-16
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yao-Wen Chang , Tsung-Hsueh Yang
IPC分类号： H01L43/02 , H01L43/12 , H01L43/08
CPC分类号： H01L43/02 , H01L43/08 , H01L43/12
摘要： The present application relates to a method for forming a top-electrode cap structure on a memory cell. In some embodiments, a method for forming a top-electrode cap structure on a memory cell. The method includes providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes. An etch is performed into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell. A getter layer is then formed to line the via opening, and further, over and abutting the top electrode of the memory cell. An oxygen-resistant layer is formed over and abutting the getter layer.

5. 发明授权

US09711508B2 Capacitor structure and method of manufacturing the same 有权
公开(公告)号：US09711508B2
公开(公告)日：2017-07-18
申请号：US14632569
申请日：2015-02-26
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Tsung-Hsueh Yang , Chung-Chiang Min , Chang-Ming Wu , Shih-Chang Liu
IPC分类号： H01L27/108 , H01L49/02
CPC分类号： H01L27/10808 , H01L27/10852 , H01L28/90
摘要： A capacitor structure includes a deep trench, a contact plug, a spacer and a metal-insulator-metal film. The deep trench extends into a crown oxide substrate, and the contact plug is disposed entirely below the crown oxide substrate. The spacer lines the deep trench, and the metal-insulator-metal film is disposed in the deep trench.

6. 发明授权

US09536969B2 Self-aligned split gate flash memory 有权
标题翻译：自对准分裂门闪存
公开(公告)号：US09536969B2
公开(公告)日：2017-01-03
申请号：US14493568
申请日：2014-09-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Tsung-Hsueh Yang , Chung-Chiang Min , Chang-Ming Wu , Shih-Chang Liu
IPC分类号： H01L29/792 , H01L29/423 , H01L27/115
CPC分类号： H01L29/42344 , H01L27/1157 , H01L29/792
摘要： The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.
摘要翻译：本公开涉及自对准分离门存储器单元及其相关方法。自对准分离栅极存储单元具有立方形形状的存储栅极，并且通过一些间隔物选择栅极覆盖的上表面。因此，存储器栅极和选择栅极被保护以防止硅化物。存储器栅极和选择栅极被所述间隔物自对准地限定。存储栅极和选择栅极通过蚀刻不被间隔物覆盖的相应导电材料而不是凹陷工艺而形成。因此，存储器栅极和选择栅极具有平坦的上表面并且被明确定义。所公开的装置和方法还能够进一步缩放，因为光刻工艺被减少。

7. 发明授权

US10164181B2 Sidewall protection of memory cell 有权
公开(公告)号：US10164181B2
公开(公告)日：2018-12-25
申请号：US15489863
申请日：2017-04-18
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Tsung-Hsueh Yang , Yuan-Tai Tseng , Yi-Jen Tsai , Shih-Chang Liu
IPC分类号： H01L45/00 , H01L43/08
摘要： A memory device includes a bottom electrode, a resistance switching element, a top electrode, a spacer and a conductive feature. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching electrode. The spacer abuts the resistance switching element. The conductive feature is over the top electrode. The spacer is at least partially between the conductive feature and the top electrode.

8. 发明申请

US20170125434A1 METHOD TO CONTROL THE COMMON DRAIN OF A PAIR OF CONTROL GATES AND TO IMPROVE INTER-LAYER DIELECTRIC (ILD) FILLING BETWEEN THE CONTROL GATES 审中-公开
公开(公告)号：US20170125434A1
公开(公告)日：2017-05-04
申请号：US15408994
申请日：2017-01-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chung-Chiang Min , Tsung-Hsueh Yang , Chang-Ming Wu , Shih-Chang Liu
IPC分类号： H01L27/11568 , H01L29/423 , H01L21/033 , H01L21/3213 , H01L21/321 , H01L29/792 , H01L21/768 , H01L21/311 , H01L21/265 , H01L29/66 , H01L29/08 , H01L21/28 , H01L21/3105
CPC分类号： H01L27/11568 , H01L21/0332 , H01L21/0337 , H01L21/26513 , H01L21/28282 , H01L21/31051 , H01L21/31111 , H01L21/32115 , H01L21/32139 , H01L21/76897 , H01L29/0847 , H01L29/42344 , H01L29/66833 , H01L29/792
摘要： A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

9. 发明授权

US09570457B2 Method to control the common drain of a pair of control gates and to improve inter-layer dielectric (ILD) filling between the control gates 有权
标题翻译：控制一对控制栅极的共同漏极并改善控制栅之间的层间电介质（ILD）填充的方法
公开(公告)号：US09570457B2
公开(公告)日：2017-02-14
申请号：US14468410
申请日：2014-08-26
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chung-Chiang Min , Tsung-Hsueh Yang , Chang-Ming Wu , Shih-Chang Liu
IPC分类号： H01L27/115 , H01L29/792 , H01L29/66 , H01L21/28 , H01L21/033 , H01L21/311 , H01L21/3105 , H01L29/423
CPC分类号： H01L27/11568 , H01L21/0332 , H01L21/0337 , H01L21/26513 , H01L21/28282 , H01L21/31051 , H01L21/31111 , H01L21/32115 , H01L21/32139 , H01L21/76897 , H01L29/0847 , H01L29/42344 , H01L29/66833 , H01L29/792
摘要： A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.
摘要翻译：提供了具有非对称轮廓的硬掩模的分裂栅极闪存单元器件的半导体结构。半导体结构的半导体衬底包括第一源极/漏极区域和第二源极/漏极区域。半导体结构的控制栅极和存储栅极在第一和第二源极/漏极区之间的半导体衬底上间隔开。半导体结构的电荷捕获电介质结构被布置在存储器栅极的相邻侧壁和控制栅极之间，并且布置在存储器栅极下方。半导体结构的硬掩模布置在控制栅极上并且包括不对称轮廓。不对称轮廓在远离记忆门的高度逐渐变细。还提供了一种用于制造具有不对称轮廓的硬掩模的一对分裂栅极闪存单元器件的方法。

10. 发明授权

US08853768B1 Method of fabricating MONOS semiconductor device 有权
标题翻译：制造MONOS半导体器件的方法
公开(公告)号：US08853768B1
公开(公告)日：2014-10-07
申请号：US13798393
申请日：2013-03-13
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chung-Chiang Min , Tsung-Hsueh Yang , Shih-Chang Liu , Chia-Shiung Tsai
IPC分类号： H01L29/792 , H01L21/336 , H01L21/28
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11568 , H01L29/42324 , H01L29/7881
摘要： A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate structures having asymmetric sidewalls including a tall side and a short side. Adjacent ones of the plurality of gate structures are separated by a tall side-tall side region and a short side-short side region. The method further comprises forming a spacer layer over the plurality of gate structures and a bottom surface of the tall side-tall side region and the short side-short side region, depositing an oxide layer over the spacer layer, etching the bottom surface portions of the oxide layer, and selectively etching the sidewall portions of the oxide layer in the tall side-tall side region.
摘要翻译：提供一种制造半导体器件的方法。该方法包括形成具有包括高边和短边的不对称侧壁的多个栅极结构。多个栅极结构中的相邻的栅极结构被一个高的侧边侧区域和短侧边区域隔开。所述方法还包括在所述多个栅极结构上形成间隔层，以及在所述高侧边侧区域和所述短边侧短边区域的底表面上形成间隔层，在所述间隔层上方沉积氧化物层，氧化物层，并且选择性地蚀刻位于高侧高侧区域中的氧化物层的侧壁部分。

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