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1. 发明授权

US11296100B2 Cell boundary structure for embedded memory 有权
公开(公告)号：US11296100B2
公开(公告)日：2022-04-05
申请号：US16908991
申请日：2020-06-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ming Chyi Liu , Shih-Chang Liu , Sheng-Chieh Chen , Yu-Hsing Chang
IPC分类号： H01L27/11521 , H01L21/28 , H01L27/11534 , H01L27/11548 , H01L21/762 , H01L27/11526 , H01L29/423 , H01L23/528
摘要： Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

2. 发明申请

US20200321345A1 CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY 审中-公开
公开(公告)号：US20200321345A1
公开(公告)日：2020-10-08
申请号：US16908991
申请日：2020-06-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ming Chyi Liu , Shih-Chang Liu , Sheng-Chieh Chen , Yu-Hsing Chang
IPC分类号： H01L27/11521 , H01L21/28 , H01L27/11534 , H01L27/11548 , H01L21/762 , H01L27/11526 , H01L29/423
摘要： Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

3. 发明授权

US09391151B2 Split gate memory device for improved erase speed 有权
标题翻译：分离门存储器件，以提高擦除速度
公开(公告)号：US09391151B2
公开(公告)日：2016-07-12
申请号：US14493538
申请日：2014-09-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chang-Ming Wu , Tsung-Hsueh Yang , Sheng-Chieh Chen , Shih-Chang Liu
IPC分类号： H01L29/788 , H01L29/423 , H01L27/115 , H01L21/28
CPC分类号： H01L29/42328 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/788 , H01L29/7881
摘要： Some embodiments relate to a memory device with an asymmetric floating gate geometry. A control gate is arranged over a floating gate. An erase gate is arranged laterally adjacent the floating gate, and is separated from the floating gate by a tunneling dielectric layer. A sidewall spacer is arranged along a vertical sidewall of the control gate, and over an upper surface of the floating gate. A portion of the floating gate upper surface forms a “ledge,” or a sharp corner, which extends horizontally past the sidewall spacer. A sidewall of the floating gate forms a concave surface, which tapers down from the ledge towards a neck region within the floating gate. The ledge provides a faster path for tunneling of the electrons through the tunneling dielectric layer compared to a floating gate with a planar sidewall surface. The ledge consequently improves the erase speed of the memory device.
摘要翻译：一些实施例涉及具有不对称浮动门几何形状的存储器件。控制门布置在浮动门上。擦除栅极横向布置在浮动栅极附近，并且通过隧道电介质层与浮动栅极分离。侧壁间隔件沿着控制栅极的垂直侧壁并且在浮动栅极的上表面上方布置。浮动门上表面的一部分形成水平延伸通过侧壁间隔物的“凸缘”或尖角。浮动栅极的侧壁形成凹入表面，其从凸缘向下朝向浮动门内的颈部区域逐渐变细。与具有平面侧壁表面的浮动栅极相比，该凸缘提供了更快的隧道隧道隧穿隧道介电层的路径。因此，该凸起因此提高了存储器件的擦除速度。

4. 发明授权

US10903366B1 Forming fin-FET semiconductor structures 有权
公开(公告)号：US10903366B1
公开(公告)日：2021-01-26
申请号：US16573888
申请日：2019-09-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sheng-Chieh Chen , Ming-Chyi Liu
IPC分类号： H01L29/78 , H01L27/1157 , H01L29/66 , H01L29/792 , H01L29/423 , H01L21/28
摘要： A process is provided to fabricate a finFET device. A gate electrode layer is positioned over a dielectric layer. The gate electrode layer and the dielectric layer are both positioned over and surrounding a fin-shaped semiconductor structure. A gate electrode is formed from the gate electrode layer through a two-step patterning process. At a first patterning step, an upper portion of the gate electrode layer is patterned. Then a dielectric film is formed covering the patterned upper portion of the gate electrode layer. After the dielectric film is formed, a second patterning process is performed to pattern a lower portion of gate electrode layer.

5. 发明授权

US10535671B2 Cell boundary structure for embedded memory 有权
公开(公告)号：US10535671B2
公开(公告)日：2020-01-14
申请号：US16506207
申请日：2019-07-09
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ming Chyi Liu , Shih-Chang Liu , Sheng-Chieh Chen , Yu-Hsing Chang
IPC分类号： H01L21/762 , H01L27/11521 , H01L21/28 , H01L27/11534 , H01L27/11548 , H01L27/11526 , H01L29/423 , H01L23/528
摘要： Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

6. 发明授权

US10461089B2 Cell boundary structure for embedded memory 有权
公开(公告)号：US10461089B2
公开(公告)日：2019-10-29
申请号：US16167879
申请日：2018-10-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ming Chyi Liu , Shih-Chang Liu , Sheng-Chieh Chen , Yu-Hsing Chang
IPC分类号： H01L27/11521 , H01L21/762 , H01L27/11526 , H01L29/423 , H01L21/28 , H01L27/11534 , H01L27/11548 , H01L23/528
摘要： Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

7. 发明申请

US20180151579A1 CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY 审中-公开
公开(公告)号：US20180151579A1
公开(公告)日：2018-05-31
申请号：US15694098
申请日：2017-09-01
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ming Chyi Liu , Shih-Chang Liu , Sheng-Chieh Chen , Yu-Hsing Chang
IPC分类号： H01L27/11521 , H01L27/11526 , H01L21/762 , H01L29/423
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/762 , H01L23/528 , H01L27/11526 , H01L27/11534 , H01L27/11548 , H01L29/42328
摘要： Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

8. 发明授权

US09978761B2 Self-aligned flash memory device 有权
公开(公告)号：US09978761B2
公开(公告)日：2018-05-22
申请号：US15216872
申请日：2016-07-22
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ming-Chyi Liu , Shih-Chang Liu , Sheng-Chieh Chen
IPC分类号： H01L27/105 , H01L27/11526 , H01L27/11519 , H01L27/11521 , H01L27/11556
CPC分类号： H01L27/11526 , H01L27/1052 , H01L27/11519 , H01L27/11521 , H01L27/11556 , H01L29/42328
摘要： The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and associated processing methods. In some embodiments, the flash memory device includes a gate stack separated from a substrate by a gate dielectric. The gate stack includes a control gate separated from a floating gate by a control gate dielectric. An erase gate is disposed on a first side of the gate stack and a word line is disposed on a second side of the gate stack that is opposite to the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. A word line height at the outer side is smaller than an erase gate height.

9. 发明授权

US11171147B2 Flash memory with improved gate structure and a method of creating the same 有权
公开(公告)号：US11171147B2
公开(公告)日：2021-11-09
申请号：US16359027
申请日：2019-03-20
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sheng-Chieh Chen , Ming Chyi Liu , Shih-Chang Liu
IPC分类号： H01L27/11517 , H01L27/11563
摘要： Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.

10. 发明申请

US20190333921A1 CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY 审中-公开
公开(公告)号：US20190333921A1
公开(公告)日：2019-10-31
申请号：US16506207
申请日：2019-07-09
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ming Chyi Liu , Shih-Chang Liu , Sheng-Chieh Chen , Yu-Hsing Chang
IPC分类号： H01L27/11521 , H01L21/762 , H01L27/11548 , H01L27/11534 , H01L21/28 , H01L29/423 , H01L27/11526
摘要： Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

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