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1. 发明授权

US11410952B2 Filter and capacitor using redistribution layer and micro bump layer 有权
公开(公告)号：US11410952B2
公开(公告)日：2022-08-09
申请号：US16923574
申请日：2020-07-08
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00
摘要： An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.

2. 发明授权

US10521538B2 Method and system for integrated circuit design with on-chip variation and spatial correlation 有权
公开(公告)号：US10521538B2
公开(公告)日：2019-12-31
申请号：US15335091
申请日：2016-10-26
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Katherine Chiang , Cheng Hsiao , Chang-Yu Huang , Juan Yi Chen , Ke-Wei Su , Chung-Kai Lin , Lester Chang , Min-Chie Jeng
IPC分类号： H01J37/32 , G06F17/50 , G06F7/58
摘要： An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

3. 发明申请

US20140278197A1 4 Port L-2L De-Embedding Method 有权
标题翻译： 4端口L-2L解嵌方法
公开(公告)号：US20140278197A1
公开(公告)日：2014-09-18
申请号：US13864376
申请日：2013-04-17
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
发明人： Hsiao-Tsung Yen , Chin-Wei Kuo , Chih-Yuan Chang , Min-Chie Jeng
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L22/30 , G01R31/2607 , G01R31/27 , H01L22/34
摘要： Some embodiments relate to a wafer. The wafer includes a first dummy component comprising two or more first dummy component transmission lines. One of the first dummy component transmission lines operably couples a first signal test pad to a second signal test pad, and an other of the first dummy component transmission lines operably couples a third signal test pad to a fourth signal test pad. A second dummy component comprises two or more second dummy component transmission lines. One of the second dummy component transmission lines operably couples a fifth signal test pad to a sixth signal test pad, and an other of the second dummy component transmission lines operably couples a seventh signal test pad to an eighth signal test pad. Other embodiments are also disclosed.
摘要翻译：一些实施例涉及晶片。该晶片包括包含两个或更多个第一虚拟部件传输线的第一虚拟部件。第一虚拟部件传输线之一可操作地将第一信号测试焊盘耦合到第二信号测试焊盘，并且第一虚设部件传输线中的另一个可操作地将第三信号测试焊盘耦合到第四信号测试焊盘。第二虚拟部件包括两个或更多个第二虚拟部件传输线。第二虚拟部件传输线之一可操作地将第五信号测试焊盘耦合到第六信号测试焊盘，并且第二虚设部件传输线中的另一个可操作地将第七信号测试焊盘耦合到第八信号测试焊盘。还公开了其他实施例。

4. 发明申请

US20210082848A1 Methods and Apparatus for Transmission Lines in Packages 有权
公开(公告)号：US20210082848A1
公开(公告)日：2021-03-18
申请号：US17098602
申请日：2020-11-16
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Wei Kuo , Hsiao-Tsung Yen , Min-Chie Jeng , Yu-Ling Lin
IPC分类号： H01L23/00 , H01L23/525 , H01L23/498 , H01L23/66 , H01L23/522 , H01L21/56 , H01L25/065
摘要： Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.

5. 发明申请

US20200125782A1 Method and System for Integrated Circuit Design With On-Chip Variation and Spatial Correlation 审中-公开
公开(公告)号：US20200125782A1
公开(公告)日：2020-04-23
申请号：US16721255
申请日：2019-12-19
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Katherine Chiang , Cheng Hsiao , Chang-Yu Huang , Juan Yi Chen , Ke-Wei Su , Chung-Kai Lin , Lester Chang , Min-Chie Jeng
IPC分类号： G06F30/39 , G06F7/58 , G06F30/367
摘要： An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

6. 发明授权

US10216879B1 Method for establishing aging model of device and analyzing aging state of device with aging model 有权
公开(公告)号：US10216879B1
公开(公告)日：2019-02-26
申请号：US15682863
申请日：2017-08-22
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yi-Shun Huang , Wai-Kit Lee , Ya-Chin Liang , Cheng Hsiao , Juan-Yi Chen , Li-Chung Hsu , Ting-Sheng Huang , Ke-Wei Su , Chung-Kai Lin , Min-Chie Jeng
IPC分类号： G06F17/50 , G06F17/30 , H01L21/66
摘要： A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.

7. 发明授权

US08941212B2 Helical spiral inductor between stacking die 有权
标题翻译：螺旋电感在堆叠模具之间
公开(公告)号：US08941212B2
公开(公告)日：2015-01-27
申请号：US13760551
申请日：2013-02-06
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hsiao-Tsung Yen , Cheng-Wei Luo , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01L21/84 , H01L27/08 , H01L21/82
CPC分类号： H01L27/08 , H01F17/0013 , H01F2017/002 , H01F2017/0086 , H01L21/82 , H01L23/5227 , H01L23/645 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L28/10 , H01L2224/0401 , H01L2224/05548 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05568 , H01L2224/0566 , H01L2224/06181 , H01L2224/13147 , H01L2224/13184 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81203 , H01L2225/06513 , H01L2225/06527 , H01L2924/15311 , H01L2924/19015 , H01L2924/19042 , H01L2924/00
摘要： The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies.
摘要翻译：本公开涉及提供良好的电感和Q因子的多电平集成电感器。在一些实施例中，集成电感器具有第一电感结构，其中第一金属层以第一螺旋图案设置在第一IC管芯上，第二电感结构具有以第二螺旋图案设置在第二IC管芯上的第二金属层。第一IC芯片垂直堆叠在第二IC芯片上。导电互连结构垂直地位于第一和第二IC芯片之间并将第一金属层电连接到第二金属层。导电互连结构提供在第一和第二电感结构之间相对较大的距离，其提供在大范围频率上具有高Q因子的电感。

8. 发明授权

US11978712B2 Method of forming semiconductor package transmission lines with micro-bump lines 有权
公开(公告)号：US11978712B2
公开(公告)日：2024-05-07
申请号：US17098602
申请日：2020-11-16
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Wei Kuo , Hsiao-Tsung Yen , Min-Chie Jeng , Yu-Ling Lin
IPC分类号： H01L21/768 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/367 , H01L23/495 , H01L23/498 , H01L23/522 , H01L23/525 , H01L23/528 , H01L23/532 , H01L23/66 , H01L25/065 , H01P5/02
CPC分类号： H01L24/11 , H01L21/563 , H01L23/49811 , H01L23/49822 , H01L23/5225 , H01L23/525 , H01L23/66 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L23/53223 , H01L23/53238 , H01L23/53257 , H01L23/5329 , H01L2223/6627 , H01L2924/0002 , H01L2924/01028 , H01L2924/01029 , H01L2924/014 , H01P5/028 , Y10T29/49124 , H01L2924/0002 , H01L2924/0001 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.

9. 发明授权

US11145767B2 Semiconductor structure 有权
公开(公告)号：US11145767B2
公开(公告)日：2021-10-12
申请号：US16834312
申请日：2020-03-30
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Chewn-Pu Jou , Min-Chie Jeng
IPC分类号： H01L31/00 , H01L21/00 , H01L29/94 , H01L29/66 , H01L21/66 , H01L27/06 , H01L49/02 , H01L23/48 , H01L23/58
摘要： A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.

10. 发明授权

US09385246B2 Differential MOSCAP device 有权
标题翻译：差分MOSCAP器件
公开(公告)号：US09385246B2
公开(公告)日：2016-07-05
申请号：US14594201
申请日：2015-01-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01L29/94 , H01L23/522 , H01L49/02
CPC分类号： H01L29/94 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A differential MOS capacitor includes a first plurality of upper capacitor plates, a second plurality of upper capacitor plates, and a conductive plate. At least two of the second plurality of upper capacitor plates are spaced laterally from each other and are disposed laterally between at least two of the first plurality of upper capacitor plates. The conductive plate is configured to serve as a common bottom capacitor plate such that a first capacitor is formed by the first plurality of upper capacitor plates and the conductive plate and a second capacitor is formed by the second plurality of upper capacitor plates and the conductive plate.
摘要翻译：差分MOS电容器包括第一多个上电容器板，第二多个上电容器板和导电板。第二组多个上部电容器板中的至少两个彼此横向隔开并横向设置在第一组多个上部电容器板中的至少两个之间。导电板被配置为用作公共底部电容器板，使得第一电容器由第一多个上电容器板和导电板形成，并且第二电容器由第二多个上电容器板和导电板形成。

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